/* Autogenerated SDM App PLL setup by dco_model.py using 24.576_1M profile */
/* Input freq: 24000000
   F: 146
   R: 0
   f: 4
   p: 10
   OD: 5
   ACD: 5
*/

#define APP_PLL_CTL_REG 0x0A809200
#define APP_PLL_DIV_REG 0x80000005
#define APP_PLL_FRAC_REG 0x8000040A
#define SW_PLL_SDM_CTRL_MID 478151
#define SW_PLL_SDM_RATE 1000000
