@@ -376,14 +376,133 @@ int i2c_codec_mic_vol_down(void)
return 0;
}
// tile 0
void AudioHwRemote2(chanend c, client interface i2c_master_if i2c);
void AudioHwRemote(chanend c)
extern void button_task(chanend c_hidSendData, chanend cc_mic_level, chanend c_uac_vol);
void AudioHwRemote(chanend c_hidSendData, chanend cc_mic_level, chanend c_uac_vol)
{
delay_milliseconds(200);
i2c_master_if i2c[1];
par {
i2c_master(i2c, 1, p_scl, p_sda, 100);
AudioHwRemote2(c, i2c[0]);
}
{
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0x00, i2c[0]);
// Initiate SW reset (PLL is powered off as part of reset)
CODEC_IC_REGWRITE(AIC3204_SW_RST, 0x01, i2c[0]);
// Program clock settings
// Default is CODEC_CLKIN is from MCLK pin. Don't need to change this.
// Power up NDAC and set to 1
CODEC_IC_REGWRITE(AIC3204_NDAC, 0x81, i2c[0]);
// Power up MDAC and set to 4
CODEC_IC_REGWRITE(AIC3204_MDAC, 0x84, i2c[0]);
// Power up NADC and set to 1
CODEC_IC_REGWRITE(AIC3204_NADC, 0x81, i2c[0]);
// Power up MADC and set to 4
CODEC_IC_REGWRITE(AIC3204_MADC, 0x84, i2c[0]);
// Program DOSR = 128
CODEC_IC_REGWRITE(AIC3204_DOSR_LSB, 0x80, i2c[0]);
// Program AOSR = 128
CODEC_IC_REGWRITE(AIC3204_AOSR, 0x80, i2c[0]);
// Set Audio Interface Config: I2S, 24 bits, slave mode, DOUT always driving.
CODEC_IC_REGWRITE(AIC3204_CODEC_IF, 0x20, i2c[0]);
// Program the DAC processing block to be used - PRB_P1
CODEC_IC_REGWRITE(AIC3204_DAC_SIG_PROC, 0x01, i2c[0]);
// Program the ADC processing block to be used - PRB_R1
CODEC_IC_REGWRITE(AIC3204_ADC_SIG_PROC, 0x01, i2c[0]); // 3D-------------------------
// Select Page 1
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0x01, i2c[0]);
// Enable the internal AVDD_LDO:
CODEC_IC_REGWRITE(AIC3204_LDO_CTRL, 0x09, i2c[0]);
//
// Program Analog Blocks
// ---------------------
//
// Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO
CODEC_IC_REGWRITE(AIC3204_PWR_CFG, 0x08, i2c[0]);
// Enable Master Analog Power Control
CODEC_IC_REGWRITE(AIC3204_LDO_CTRL, 0x01, i2c[0]);
// Set Common Mode voltages: Full Chip CM to 0.9V and Output Common Mode for Headphone to 1.65V and HP powered from LDOin @ 3.3V.
CODEC_IC_REGWRITE(AIC3204_CM_CTRL, 0x33, i2c[0]);
// Set PowerTune Modes
// Set the Left & Right DAC PowerTune mode to PTM_P3/4. Use Class-AB driver.
CODEC_IC_REGWRITE(AIC3204_PLAY_CFG1, 0x00, i2c[0]);
CODEC_IC_REGWRITE(AIC3204_PLAY_CFG2, 0x00, i2c[0]);
// Set ADC PowerTune mode PTM_R4.
CODEC_IC_REGWRITE(AIC3204_ADC_PTM, 0x00, i2c[0]);
// Set MicPGA startup delay to 3.1ms
CODEC_IC_REGWRITE(AIC3204_AN_IN_CHRG, 0x31, i2c[0]);
// Set the REF charging time to 40ms
CODEC_IC_REGWRITE(AIC3204_REF_STARTUP, 0x01, i2c[0]);
// HP soft stepping settings for optimal pop performance at power up
// Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling
// capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
CODEC_IC_REGWRITE(AIC3204_HP_START, 0x25, i2c[0]);
// Route Left DAC to HPL
CODEC_IC_REGWRITE(AIC3204_HPL_ROUTE, 0x08, i2c[0]);
// Route Right DAC to HPR
CODEC_IC_REGWRITE(AIC3204_HPR_ROUTE, 0x08, i2c[0]);
CODEC_IC_REGWRITE(0x0e, 0x08, i2c[0]);
CODEC_IC_REGWRITE(0x0f, 0x08, i2c[0]);
CODEC_IC_REGWRITE(0x12, 0x3a, i2c[0]);
CODEC_IC_REGWRITE(0x13, 0x3a, i2c[0]); //Gain-0DB
// We are using Line input with low gain for PGA so can use 40k input R but lets stick to 20k for now.
// Route IN2_L to LEFT_P with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_LPGA_P_ROUTE, 0x20, i2c[0]); //---
// Route IN2_R to LEFT_M with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_LPGA_N_ROUTE, 0x20, i2c[0]); //---
// Route IN1_R to RIGHT_P with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_RPGA_P_ROUTE, 0x80, i2c[0]); //---
// Route IN1_L to RIGHT_M with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_RPGA_N_ROUTE, 0x20, i2c[0]); //---
// Unmute HPL and set gain to 0dB
CODEC_IC_REGWRITE(AIC3204_HPL_GAIN, 0x06, i2c[0]);
// Unmute HPR and set gain to 0dB
CODEC_IC_REGWRITE(AIC3204_HPR_GAIN, 0x06, i2c[0]);
// Unmute Left MICPGA, Set Gain to 0dB.
CODEC_IC_REGWRITE(AIC3204_LPGA_VOL, 0x00, i2c[0]);
// Unmute Right MICPGA, Set Gain to 0dB.
CODEC_IC_REGWRITE(AIC3204_RPGA_VOL, 0x00, i2c[0]);
// Power up HPL and HPR drivers
CODEC_IC_REGWRITE(AIC3204_OP_PWR_CTRL, 0x30, i2c[0]); // HP powerUp
//CODEC_REGWRITE(AIC3204_OP_PWR_CTRL, 0x0C); // LO powerUP
// Wait for 2.5 sec for soft stepping to take effect
//vTaskDelay(pdMS_TO_TICKS(2500));
delay_milliseconds(10);
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0x00, i2c[0]);
// Power up the Left and Right DAC Channels. Route Left data to Left DAC and Right data to Right DAC.
// DAC Vol control soft step 1 step per DAC word clock.
CODEC_IC_REGWRITE(AIC3204_DAC_CH_SET1, 0xd4, i2c[0]);
// Power up Left and Right ADC Channels, ADC vol ctrl soft step 1 step per ADC word clock.
CODEC_IC_REGWRITE(AIC3204_ADC_CH_SET, 0xc0, i2c[0]);
// Unmute Left and Right DAC digital volume control
CODEC_IC_REGWRITE(AIC3204_DAC_CH_SET2, 0x00, i2c[0]);
// Unmute Left and Right ADC Digital Volume Control.
CODEC_IC_REGWRITE(AIC3204_ADC_FGA_MUTE, 0x00, i2c[0]);
CODEC_IC_REGWRITE( AIC3204_PAGE_CTRL, 1, i2c[0]); //page1
CODEC_IC_REGWRITE( 0x47, 0x32, i2c[0]); //analog input quick charging configure
CODEC_IC_REGWRITE( 0x7b, 0x01, i2c[0]); //power up config
CODEC_IC_REGWRITE( 0x33, 0x60, i2c[0]); //---------0x78 used fail-------jian added ----MICBIAS
CODEC_IC_REGWRITE( 0x37, 0x80, i2c[0]);
CODEC_IC_REGWRITE( 0x39, 0x20, i2c[0]); // IN1L to RIGHT MICPGA with 20k ohm
CODEC_IC_REGWRITE( 0x3c, mic_vol/*40*/, i2c[0]); // Right MICPGA VOL --5a-45DB 5e--47db :3d--ap实际测试25DB增益---跟客户样品一致 （ ）
CODEC_IC_REGWRITE( AIC3204_PAGE_CTRL, 0, i2c[0]); // page0
CODEC_IC_REGWRITE( 0x51, 0xc0, i2c[0]); //
CODEC_IC_REGWRITE( 0x52, 0x00, i2c[0]); //
i2c[0].shutdown();
}
}
button_task(c_hidSendData, cc_mic_level, c_uac_vol);
}
#define EQ_MODE_DELAY (20000000) //100ms delay
@@ -400,24 +519,11 @@ void AudioHwRemote2(chanend c, client interface i2c_master_if i2c)
eq_mode_time += EQ_MODE_DELAY;
eq_sync_timer :> eq_sync_time;
eq_sync_time += EQ_SYNC_DELAY;
}
while (1) {
select {
case c :> cmd:
if (cmd == AUDIOHW_CMD_REGRD) {
unsigned regAddr, regVal;
c:>regAddr;
CODEC_IC_REGREAD(regAddr, regVal, i2c);
c<:regVal;
} else {
unsigned regAddr, regVal;
c:>regAddr;
c:>regVal;
CODEC_IC_REGWRITE(regAddr, regVal, i2c);
}
break;
#if EQ_EN
if EQ_EN
case eq_mode_timer when timerafter(eq_mode_time) :> void :
eq_mode_time += EQ_MODE_DELAY;
unsigned request_eq_mode, new_eq_mode;
@@ -466,239 +572,18 @@ void AudioHwRemote2(chanend c, client interface i2c_master_if i2c)
#endif
}
}
}
int adc_2ch_48K_highPerformance(void)
{
#if defined (CODEC_AIC3204)
debug_printf("adc_2ch_48K_highPerformance");
//0==CODEC_REGWRITE( AIC3204_PAGE_CTRL, 0) // page0
//CODEC_REGWRITE( AIC3204_SW_RST, 1); //Set
//&& 0== CODEC_REGWRITE( 0x12, 0x81) //NADC
//&& 0== CODEC_REGWRITE( 0x13, 0x84) //MADC
//&& 0== CODEC_REGWRITE( 0x14, 0x40) //AOSR
//&& 0== CODEC_REGWRITE( 0x1d, 0x10) // dac route2 adc-----jian added ---LoopBack
//&&
CODEC_REGWRITE( AIC3204_PAGE_CTRL, 1); //page1
//&& 0== CODEC_REGWRITE( 0x0c, 0x04) //IN1L-route2--HPL----------
//&& 0== CODEC_REGWRITE( 0x01, 0x08)
//&& 0== CODEC_REGWRITE( 0x02, 0)
//&& 0== CODEC_REGWRITE( 0x0a, 0x40)// ---- 0x00
//&& 0== CODEC_REGWRITE( 0x3d, 0xff)// ---- 0x00
CODEC_REGWRITE( 0x47, 0x32); //analog input quick charging configure
CODEC_REGWRITE( 0x7b, 0x01); //power up config
//CODEC_REGWRITE(AIC3204_LPGA_P_ROUTE, 0x20) == 0 &&
// Route IN2_R to LEFT_M with 20K input impedance
//CODEC_REGWRITE(AIC3204_LPGA_N_ROUTE, 0x20) == 0 &&
CODEC_REGWRITE( 0x33, 0x60); //---------0x78 used fail-------jian added ----MICBIAS
//Route IN1L to LEFT_P with 20K input impedance
//&& 0== CODEC_REGWRITE( 0x34, 0x00)
//&& 0== CODEC_REGWRITE( 0x34, 0x80) // 0x80-fail
//&& 0== CODEC_REGWRITE( 0x36, 0x80) // 0x80-fail
CODEC_REGWRITE( 0x37, 0x80);
CODEC_REGWRITE( 0x39, 0x20); // IN1L to RIGHT MICPGA with 20k ohm
//&& 0== CODEC_REGWRITE( 0x3b, 0x5f) // Left MICPGA VOL--------------
CODEC_REGWRITE( 0x3c, mic_vol/*40*/); // Right MICPGA VOL --5a-45DB 5e--47db :3d--ap实际测试25DB增益---跟客户样品一致 （ ）
#if 1 //added _jian
//&& 0== CODEC_REGWRITE( 0x3e, 0x02)
//&& 0== CODEC_REGWRITE( AIC3204_PAGE_CTRL, 8) //page1
//&& 0== CODEC_REGWRITE( 1, 4) // adc adaptive filter
#endif
CODEC_REGWRITE( AIC3204_PAGE_CTRL, 0); // page0
//CODEC_REGWRITE( 0x35, 0x02); //default-0x00 DOUT: 02:loopbak
//CODEC_REGWRITE( 0x35, 0x12); //default-0x02 DOUT
//CODEC_REGWRITE( 0x53, 0x08); // _jian L_ADC volume 20DB 录到一条直线
//CODEC_REGWRITE( 0x54, 0x28); // _jian R_ADC volume 20DB
CODEC_REGWRITE( 0x51, 0xc0); //
CODEC_REGWRITE( 0x52, 0x00); //
#endif
return 0;
}
/// @brief
/// @param
/// @return
int i2c_codec_setup(void)
{
// Take dac out of reset
// dac_reset_inactive(i2c);---------
// Reset recovery time
delay_milliseconds(20);
//const rtos_gpio_port_id_t codec_rst_port = rtos_gpio_port(PORT_CODEC_RST_N);
//rtos_gpio_port_enable(gpio_ctx_t1, codec_rst_port);
//rtos_gpio_port_out(gpio_ctx_t1, codec_rst_port, 0xF);
#if defined (CODEC_AIC3204)
// Set register page to 0
CODEC_REGWRITE(AIC3204_PAGE_CTRL, 0x00);
// Initiate SW reset (PLL is powered off as part of reset)
CODEC_REGWRITE(AIC3204_SW_RST, 0x01);
// Program clock settings
// Default is CODEC_CLKIN is from MCLK pin. Don't need to change this.
// Power up NDAC and set to 1
CODEC_REGWRITE(AIC3204_NDAC, 0x81);
// Power up MDAC and set to 4
CODEC_REGWRITE(AIC3204_MDAC, 0x84);
// Power up NADC and set to 1
CODEC_REGWRITE(AIC3204_NADC, 0x81);
// Power up MADC and set to 4
CODEC_REGWRITE(AIC3204_MADC, 0x84);
// Program DOSR = 128
CODEC_REGWRITE(AIC3204_DOSR_LSB, 0x80);
// Program AOSR = 128
CODEC_REGWRITE(AIC3204_AOSR, 0x80);
// Set Audio Interface Config: I2S, 24 bits, slave mode, DOUT always driving.
CODEC_REGWRITE(AIC3204_CODEC_IF, 0x20);
// Program the DAC processing block to be used - PRB_P1
CODEC_REGWRITE(AIC3204_DAC_SIG_PROC, 0x01);
// Program the ADC processing block to be used - PRB_R1
CODEC_REGWRITE(AIC3204_ADC_SIG_PROC, 0x01); // 3D-------------------------
// Select Page 1
CODEC_REGWRITE(AIC3204_PAGE_CTRL, 0x01);
// Enable the internal AVDD_LDO:
CODEC_REGWRITE(AIC3204_LDO_CTRL, 0x09);
//
// Program Analog Blocks
// ---------------------
//
// Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO
CODEC_REGWRITE(AIC3204_PWR_CFG, 0x08);
// Enable Master Analog Power Control
CODEC_REGWRITE(AIC3204_LDO_CTRL, 0x01);
// Set Common Mode voltages: Full Chip CM to 0.9V and Output Common Mode for Headphone to 1.65V and HP powered from LDOin @ 3.3V.
CODEC_REGWRITE(AIC3204_CM_CTRL, 0x33);
// Set PowerTune Modes
// Set the Left & Right DAC PowerTune mode to PTM_P3/4. Use Class-AB driver.
CODEC_REGWRITE(AIC3204_PLAY_CFG1, 0x00);
CODEC_REGWRITE(AIC3204_PLAY_CFG2, 0x00);
// Set ADC PowerTune mode PTM_R4.
CODEC_REGWRITE(AIC3204_ADC_PTM, 0x00);
// Set MicPGA startup delay to 3.1ms
CODEC_REGWRITE(AIC3204_AN_IN_CHRG, 0x31);
// Set the REF charging time to 40ms
CODEC_REGWRITE(AIC3204_REF_STARTUP, 0x01);
// HP soft stepping settings for optimal pop performance at power up
// Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling
// capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
CODEC_REGWRITE(AIC3204_HP_START, 0x25);
// Route Left DAC to HPL
CODEC_REGWRITE(AIC3204_HPL_ROUTE, 0x08);
// Route Right DAC to HPR
CODEC_REGWRITE(AIC3204_HPR_ROUTE, 0x08);
CODEC_REGWRITE(0x0e, 0x08);
CODEC_REGWRITE(0x0f, 0x08);
CODEC_REGWRITE(0x12, 0x3a);
CODEC_REGWRITE(0x13, 0x3a); //Gain-0DB
// We are using Line input with low gain for PGA so can use 40k input R but lets stick to 20k for now.
// Route IN2_L to LEFT_P with 20K input impedance
CODEC_REGWRITE(AIC3204_LPGA_P_ROUTE, 0x20); //---
// Route IN2_R to LEFT_M with 20K input impedance
CODEC_REGWRITE(AIC3204_LPGA_N_ROUTE, 0x20); //---
// Route IN1_R to RIGHT_P with 20K input impedance
CODEC_REGWRITE(AIC3204_RPGA_P_ROUTE, 0x80); //---
// Route IN1_L to RIGHT_M with 20K input impedance
CODEC_REGWRITE(AIC3204_RPGA_N_ROUTE, 0x20); //---
// Unmute HPL and set gain to 0dB
CODEC_REGWRITE(AIC3204_HPL_GAIN, 0x06);
// Unmute HPR and set gain to 0dB
CODEC_REGWRITE(AIC3204_HPR_GAIN, 0x06);
// Unmute Left MICPGA, Set Gain to 0dB.
CODEC_REGWRITE(AIC3204_LPGA_VOL, 0x00);
// Unmute Right MICPGA, Set Gain to 0dB.
CODEC_REGWRITE(AIC3204_RPGA_VOL, 0x00);
// Power up HPL and HPR drivers
CODEC_REGWRITE(AIC3204_OP_PWR_CTRL, 0x30); // HP powerUp
//CODEC_REGWRITE(AIC3204_OP_PWR_CTRL, 0x0C); // LO powerUP
// Wait for 2.5 sec for soft stepping to take effect
//vTaskDelay(pdMS_TO_TICKS(2500));
delay_milliseconds(10);
// while(1)CODEC_REGWRITE(AIC3204_PAGE_CTRL, 0x00); //for Test _jian 20250317
debug_printf("i2c_codec_setup");
//
// Power Up DAC/ADC
// ----------------
//
// Select Page 0
CODEC_REGWRITE(AIC3204_PAGE_CTRL, 0x00);
// Power up the Left and Right DAC Channels. Route Left data to Left DAC and Right data to Right DAC.
// DAC Vol control soft step 1 step per DAC word clock.
CODEC_REGWRITE(AIC3204_DAC_CH_SET1, 0xd4);
// Power up Left and Right ADC Channels, ADC vol ctrl soft step 1 step per ADC word clock.
CODEC_REGWRITE(AIC3204_ADC_CH_SET, 0xc0);
// Unmute Left and Right DAC digital volume control
CODEC_REGWRITE(AIC3204_DAC_CH_SET2, 0x00);
// Unmute Left and Right ADC Digital Volume Control.
CODEC_REGWRITE(AIC3204_ADC_FGA_MUTE, 0x00);
return 0;
#endif
}
/* Configures the external audio hardware at startup */
void AudioHwInit()
{
int result=0;
sw_pll_fixed_clock(MCLK_48);
// Wait for power supply to come up.
delay_milliseconds(100);
#if 0
/* Wait until global is set */
unsafe
{
while(!(unsigned) i_i2c_client);
}
#endif
/* Use xCORE Secondary PLL to generate *fixed* master clock */
if (DEFAULT_FREQ % 22050 == 0)
{
sw_pll_fixed_clock(MCLK_441);
}
else
{
sw_pll_fixed_clock(MCLK_48);
}
result = i2c_codec_setup();
if(result)
debug_printf("CODEC DAC Init Err");
else
debug_printf("CODEC DAC Init OK.");
result = adc_2ch_48K_highPerformance();
if(result)
debug_printf("CODEC ADC Init Err");
else
debug_printf("CODEC ADC Init OK.");
}
/* Configures the external audio hardware for the required sample frequency */
Steven Dan