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Steven Dan
2026-05-12 11:17:20 +08:00
parent b5b095efd0
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**/.build*/*
**/bin/*
*.o
*.xe
*.vcd
*.xi
*.i
*.a
**/_build/
**/run_*.log
**/pdf/*
*.pyc
test_results.csv
*.xmt
output*.dat
*.swp
.*.swp
.*.*.swp
*.swo
*.todo
org.eclipse.cdt.core.prefs
xsim.args
tests/src_output
*.bak
**/.venv/**
build/
tests/tmp
tests/vpu_ff3_test/autogen
tests/vpu_rat_test/autogen
*.csv
python/lib_src.egg-info
**/tmp_models/
*.bak
make_docs.sh

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[submodule "xmos_cmake_toolchain"]
path = xmos_cmake_toolchain
url = git@github.com:xmos/xmos_cmake_toolchain.git

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tests/asrc_test/model/ASRC.c
tests/asrc_test/model/ASRC.h
tests/asrc_test/model/FIR.c
tests/asrc_test/model/FIR.h
tests/asrc_test/model/FilterDefs.c
tests/asrc_test/model/FilterDefs.h
tests/asrc_test/model/IntArithmetic.c
tests/asrc_test/model/IntArithmetic.h
tests/asrc_test/model/Main.c
tests/asrc_test/model/Main.h
tests/ds3_test/model/FIRDS3.c
tests/ds3_test/model/FIRDS3.h
tests/ds3_test/model/IntArithmetic.c
tests/ds3_test/model/IntArithmetic.h
tests/ds3_test/model/Main.c
tests/ds3_test/model/Main.h
tests/os3_test/model/FIROS3.c
tests/os3_test/model/FIROS3.h
tests/os3_test/model/IntArithmetic.c
tests/os3_test/model/IntArithmetic.h
tests/os3_test/model/Main.c
tests/os3_test/model/Main.h
tests/ssrc_test/model/FIR.c
tests/ssrc_test/model/FIR.h
tests/ssrc_test/model/FilterDefs.c
tests/ssrc_test/model/FilterDefs.h
tests/ssrc_test/model/IntArithmetic.c
tests/ssrc_test/model/IntArithmetic.h
tests/ssrc_test/model/Main.c
tests/ssrc_test/model/Main.h
tests/ssrc_test/model/SSRC.c
tests/ssrc_test/model/SSRC.h

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lib_src change log
==================
2.5.0
-----
* ADDED: VPU enabled ASRC and SSRC providing a 2x speed improvement
* ADDED: Asynchronous FIFO with phase detector and PID rate controller for
ASRC usage
* ADDED: Support for XCommon CMake build system
* FIXED: Function pointer annotation avoid stack corruption when using
multiple instances of SSRC or ASRC.
* Changes to dependencies:
- lib_logging: 3.1.1 -> 3.2.0
- lib_xassert: Removed dependency
2.4.0
-----
* ADDED: Support for building the core ASRC code in the C emulator as a
library
* ADDED: Auto-generated ASRC and SSRC performance plots in documentation
* ADDED: Documentation warning about overflow in XS3 optimized SRC components
* CHANGED: Documents built under Jenkins instead of Github Actions
* CHANGED: Tested against fwk_core v1.0.2 updated from v1.0.0
2.3.0
-----
* ADDED: XS3 VPU optimised voice fixed factor of 3 upsampling/downsampling
* ADDED: XS3 VPU optimised voice fixed factor of 3/2 upsampling/downsampling
* CHANGED: OS3 uses firos3_144.dat coefficients by default inline with model
* CHANGED: Replaced xmostest with pytest for all SRC automated tests
* CHANGED: Used XMOS doc builder for documentation
* CHANGED: Golden reference test signals now generated automatically by CI
* RESOLVED: Linker warning on channel ends
* REMOVED: AN00231 ASRC App Note. See github.com/xmos/sln_voice/examples
* CHANGED: Increased precision of the fFsRatioDeviation used in the C emulator
from float to double
* CHANGED: Allow for 64 bits in the rate ratio passed to asrc_process() for
extra precision
* Changes to dependencies:
- lib_logging: 2.0.1 -> 3.1.1
- lib_xassert: 2.0.1 -> 4.1.0
2.2.0
-----
* CHANGED: Made the FIR coefficient array that is used with the voice fixed
factor of 3 up and down sampling functions usable from within C files as
well as XC files.
* CHANGED: Aligned the FIR coefficient array to an 8-byte boundary. This
ensures that the voice fixed factor of 3 up and down sampling functions do
not crash with a LOAD_STORE exception.
* ADDED: Missing device attributes to the .xn file of the AN00231 app note.
* ADDED: Minimal cmake support.
2.1.0
-----
* CHANGED: Use XMOS Public License Version 1
2.0.1
-----
* CHANGED: Pin Python package versions
* REMOVED: not necessary cpanfile
2.0.0
-----
* CHANGED: Build files updated to support new "xcommon" behavior in xwaf.
1.1.2
-----
* CHANGED: initialisation lists to avoid warnings when building
1.1.1
-----
* RESOLVED: correct compensation factor for voice upsampling
* ADDED: test of voice unity gain
1.1.0
-----
* ADDED: Fixed factor of 3 conversion functions for downsampling and
oversampling
* ADDED: Fixed factor of 3 downsampling function optimised for use with voice
(reduced memory and compute footprint)
* ADDED: Fixed factor of 3 upsampling function optimised for use with voice
(reduced memory and compute footprint)
1.0.0
-----
* Initial version
* Changes to dependencies:
- lib_logging: Added dependency 2.0.1
- lib_xassert: Added dependency 2.0.1

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cmake_minimum_required(VERSION 3.21.0)
project(lib_src LANGUAGES C ASM)
if(PROJECT_IS_TOP_LEVEL)
include(FetchContent)
FetchContent_Declare(
fwk_core
GIT_REPOSITORY https://github.com/xmos/fwk_core.git
GIT_TAG v1.0.2
)
FetchContent_MakeAvailable(fwk_core)
endif()
add_subdirectory(tests)
# XS3 only libraries that use the Vector Processing Unit
if(${CMAKE_SYSTEM_PROCESSOR} STREQUAL XCORE_XS3A)
## Source files
file(GLOB_RECURSE LIB_C_SOURCES_XS3 lib_src/src/fixed_factor_vpu_voice/*.c )
file(GLOB_RECURSE LIB_XC_SOURCES_XS3 lib_src/src/fixed_factor_vpu_voice/*.xc)
file(GLOB_RECURSE LIB_ASM_SOURCES_XS3 lib_src/src/fixed_factor_vpu_voice/*.S )
set(ADDITIONAL_INCLUDE_DIRS_XS3 lib_src/src/fixed_factor_vpu_voice
)
endif()
if((${CMAKE_SYSTEM_PROCESSOR} STREQUAL XCORE_XS3A) OR (${CMAKE_SYSTEM_PROCESSOR} STREQUAL XCORE_XS2A))
## Source files
file(GLOB_RECURSE LIB_C_SOURCES lib_src/src/fixed_factor_of_3/*.c
lib_src/src/fixed_factor_of_3_voice/*.c
lib_src/src/multirate_hifi/*.c
)
file(GLOB LIB_C_SOURCES_FIFO lib_src/src/*.c
)
file(GLOB_RECURSE LIB_XC_SOURCES lib_src/src/fixed_factor_of_3/*.xc
lib_src/src/fixed_factor_of_3_voice/*.xc
lib_src/src/multirate_hifi/*.xc
)
file(GLOB_RECURSE LIB_ASM_SOURCES lib_src/src/fixed_factor_of_3/*.S
lib_src/src/fixed_factor_of_3_voice/*.S
lib_src/src/multirate_hifi/*.S
)
## Create library target
add_library(lib_src STATIC EXCLUDE_FROM_ALL ${LIB_C_SOURCES}
${LIB_C_SOURCES_FIFO}
${LIB_C_SOURCES_XS3}
${LIB_ASM_SOURCES}
${LIB_XC_SOURCES_XS3}
${LIB_XC_SOURCES}
${LIB_ASM_SOURCES_XS3}
)
target_include_directories(lib_src
PUBLIC
lib_src/api
lib_src/src/fixed_factor_of_3
lib_src/src/fixed_factor_of_3/ds3
lib_src/src/fixed_factor_of_3/os3
lib_src/src/fixed_factor_of_3_voice
lib_src/src/fixed_factor_of_3_voice/ds3_voice
lib_src/src/fixed_factor_of_3_voice/us3_voice
lib_src/src/multirate_hifi
lib_src/src/multirate_hifi/asrc
lib_src/src/multirate_hifi/ssrc
${ADDITIONAL_INCLUDE_DIRS_XS3}
)
target_compile_options(lib_src
PRIVATE
-O3
-g
)
target_link_libraries(lib_src
PUBLIC
# defined in fwk_core
framework_core_legacy_compat
)
endif()

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@Library('xmos_jenkins_shared_library@v0.25.0')
def runningOn(machine) {
println "Stage running on:"
println machine
}
// run pytest with common flags for project. any passed in though extra args will
// be appended
def localRunPytest(String extra_args="") {
catchError{
sh "python -m pytest --junitxml=pytest_result.xml -rA -v --durations=0 -o junit_logging=all ${extra_args}"
}
junit "pytest_result.xml"
}
getApproval()
pipeline {
agent none
environment {
REPO = 'lib_src'
VIEW = getViewName(REPO)
PYTHON_VERSION = "3.10.5"
VENV_DIRNAME = ".venv"
XMOSDOC_VERSION = "v4.0"
}
options {
skipDefaultCheckout()
timestamps()
}
parameters {
string(
name: 'TOOLS_VERSION',
defaultValue: '15.2.1',
description: 'The XTC tools version'
)
}
stages {
stage('Build and Test') {
when {
expression { !env.GH_LABEL_DOC_ONLY.toBoolean() }
}
agent {
label 'x86_64&&docker' // These agents have 24 cores so good for parallel xsim runs
}
stages {
stage('Get repo') {
steps {
sh "mkdir ${REPO}"
// source checks require the directory
// name to be the same as the repo name
dir("${REPO}") {
// checkout repo
checkout scm
sh 'git submodule update --init --recursive --depth 1'
}
}
}
stage ("Create Python environment") {
steps {
dir("${REPO}") {
createVenv('requirements.txt')
withVenv {
sh 'pip install -r requirements.txt'
}
}
}
}
stage('Library checks') {
steps {
dir("${REPO}") {
sh 'git clone git@github.com:xmos/infr_apps.git'
sh 'git clone git@github.com:xmos/infr_scripts_py.git'
// These are needed for xmake legacy build and also changelog check
sh 'git clone git@github.com:xmos/lib_logging.git'
sh 'git clone git@github.com:xmos/lib_xassert.git'
withVenv {
sh 'pip install -e infr_scripts_py'
sh 'pip install -e infr_apps'
dir("tests") {
withEnv(["XMOS_ROOT=.."]) {
localRunPytest('-s test_lib_checks.py -vv')
}
}
}
}
}
}
stage('Test xmake build') {
steps {
runningOn(env.NODE_NAME)
dir("${REPO}") {
withTools(params.TOOLS_VERSION) {
withVenv {
dir("tests") {
localRunPytest('-k "legacy" -vv')
}
}
}
}
}
}
stage('Run doc python') {
steps {
runningOn(env.NODE_NAME)
dir("${REPO}") {
withTools(params.TOOLS_VERSION) {
withVenv {
sh "sh doc/build_docs_ci.sh $XMOSDOC_VERSION"
archiveArtifacts artifacts: "doc_build.zip", allowEmptyArchive: true
}
}
}
}
}
stage('Tests XS2') {
steps {
runningOn(env.NODE_NAME)
dir("${REPO}") {
withTools(params.TOOLS_VERSION) {
withVenv {
sh 'mkdir -p build'
dir("build") {
sh 'rm CMakeCache.txt'
sh 'cmake --toolchain ../xmos_cmake_toolchain/xs2a.cmake ..'
sh 'make test_ds3_voice test_us3_voice test_unity_gain_voice -j'
}
dir("tests") {
localRunPytest('-n auto -k "xs2" -vv')
}
dir("build") {
sh 'rm CMakeCache.txt' // Cleanup XS2 cmake cache for next stage
}
}
}
}
}
}
stage('Tests XS3') {
steps {
runningOn(env.NODE_NAME)
dir("${REPO}") {
withTools(params.TOOLS_VERSION) {
withVenv {
dir("tests") {
localRunPytest('-m prepare') // Do all pre work like building and generating golden ref where needed
// FF3 HiFi tests for OS3 and DS3
localRunPytest('-m main -n auto -k "hifi_ff3" -vv')
// ASRC and SSRC tests across all in/out freqs and deviations (asrc only)
localRunPytest('-m main -n auto -k "mrhf" -vv')
archiveArtifacts artifacts: "mips_report*.csv", allowEmptyArchive: true
// VPU enabled ff3 and rat tests
localRunPytest('-m main -k "vpu" -vv') // xdist not working yet so no -n auto
// Profile the ASRC
localRunPytest('-m main -k "profile_asrc" -vv')
sh 'tree'
archiveArtifacts artifacts: "gprof_results/*.png", allowEmptyArchive: true
}
}
}
}
}
}
}
post {
cleanup {
xcoreCleanSandbox()
}
}
}
}
}

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*******************************
XMOS PUBLIC LICENCE: Version 1
*******************************
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**“Compiled Code”** means any compiled, binary, machine readable or executable version of the Source Code.
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**“Derivatives”** means any addition to, deletion from and/or change to the substance, structure of the Software, any previous Derivatives, the combination of the Derivatives and the Software and/or any respective portions thereof.
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**“Software”** means the software and associated documentation files which XMOS makes available and which contain a notice identifying the software as original XMOS software and referring to the software being subject to the terms of this XMOS Public Licence.
This Licence refers to XMOS Software and does not relate to any XMOS hardware or devices which are protected by intellectual property rights (including patent and trade marks) which may be sold to you under a separate agreement.
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Sample Rate Conversion Library
==============================
Overview
--------
The XMOS Sample Rate Conversion (SRC) library provides both synchronous and asynchronous audio sample rate conversion functions for use on xCORE multicore micro-controllers.
In systems where the rate change is exactly equal to the ratio of nominal rates, synchronous sample rate conversion (SSRC) provides efficient and high performance rate conversion. Where the input and output rates are not locked by a common clock or clocked by an exact rational frequency ratio, the Asynchronous Sample Rate Converter (ASRC) provides a way of streaming high quality audio between the two different clock domains, at the cost of higher processing resource usage. ASRC can ease interfacing in cases where there are multiple digital audio inputs or allow cost saving by removing the need for physical clock recovery using a PLL.
Features
........
Multi-rate Hi-Fi functionality:
* Conversion between 44.1, 48, 88.2, 96, 176.4 and 192 KHz input and output sample rates.
* 32 bit PCM input and output data in Q1.31 signed format.
* Optional output dithering to 24 bit using Triangular Probability Density Function (TPDF).
* Optimized for xCORE-200 instruction set with dual-issue and compatible with XCORE-AI.
* Block based processing - Minimum 4 samples input per call, must be power of 2.
* Up to 10000 ppm sample rate ratio deviation from nominal rate (ASRC only).
* Very high quality - SNR greater than 135 dB (ASRC) or 140 dB (SSRC), with THD of less than 0.0001% (reference 1KHz).
* Configurable number of audio channels per SRC instance.
* Reentrant library permitting multiple instances with differing configurations and channel count.
* No external components (PLL or memory) required.
Fixed factor functionality:
* Synchronous fixed factor of 3 downsample and oversample functions supporting either HiFi quality or reduced resource requirements for voice applications.
* Synchronous fixed factor of 3 and 3/2 downsample and oversample functions for voice applications optimized for the XS3 Vector Processing Unit.
Building
........
The library can be built under `cmake` or `xcommon` via `xmake` offering backwards compatibility for legacy applications.
It is recommended to use `cmake` where the library name `lib_src` is included in the cmake files. See `Related application notes`_ for example usage.
The library has no dependencies when building under `cmake` although does require `lib_logging` and `lib_xassert` when using `xcommon`.
Components
..........
* Synchronous Sample Rate Converter function (ssrc)
* Asynchronous Sample Rate Converter function (asrc)
* Synchronous factor of 3 downsample function (ds3)
* Synchronous factor of 3 oversample function (os3)
* Synchronous factor of 3 downsample function optimized for use with voice (src_ds3_voice)
* Synchronous factor of 3 oversample function optimised for use with voice (src_us3_voice)
* Synchronous factor of 3 downsample function for use with voice optimized for XS3 (ff3_96t_ds)
* Synchronous factor of 3 oversample function for use with voice optimized for XS3 (ff3_96t_us)
* Synchronous factor of 3/2 downsample function for use with voice optimized for XS3 (rat_2_3_96t_ds)
* Synchronous factor of 3/2 oversample function for use with voice optimized for XS3 (rat_3_2_96t_us)
There are three different component options that support fixed factor of 3 up/downsampling. To help choose which one to use follow these steps:
#. If HiFi quality (130 dB SNR) up/downsampling is required, use ds3 or os3.
#. If voice quality (65 dB SNR) is required running on xCORE-200, use ds3_voice or us3_voice.
#. If voice quality (75 dB SNR) is required running xcore-ai, use ff3_96t_ds or ff3_96t_us.
.. warning::
Synchronous fixed factor of 3 and 3/2 downsample and oversample functions for voice applications optimized for the XS3 Vector Processing Unit
currently overflow rather than saturate in cases where a full scale input causes a perturbation above full scale at the output.
To avoid this scenario, please ensure that the input amplitude is always 3.5 dB below full scale.
The overflow behavior of these SRC components will be replaced by saturating behavior (to match all other SRC components) in a future release.
Related Application Notes
.........................
An adaptive USB Audio ASRC example can be found in https://github.com/xmos/sln_voice/tree/develop/examples.
Simple file-based test applications may be found in this repo under `tests/xxxx_test` where xxxx is either `asrc`, `ssrc`, `ds3`, `os3`, `ds3_voice`, `os3_voice`, `vpu_ff3` or `vpu_rat`.
These test applications may be used as basic examples to show how these components are used in a minimal application.

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######################
SAMPLE RATE CONVERSION
######################
.. toctree::
:maxdepth: 5
./doc/programming_guide/index.rst
./doc/python/_build/rst/allPlots.rst

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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="com.xmos.cdt.toolchain.603026229">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.xmos.cdt.toolchain.603026229" moduleId="org.eclipse.cdt.core.settings" name="Default">
<externalSettings/>
<extensions>
<extension id="com.xmos.cdt.core.XEBinaryParser" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
<extension id="com.xmos.cdt.core.XdeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
</extensions>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<configuration buildProperties="" description="" id="com.xmos.cdt.toolchain.603026229" name="Default" parent="org.eclipse.cdt.build.core.emptycfg">
<folderInfo id="com.xmos.cdt.toolchain.603026229.1562368492" name="/" resourcePath="">
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<targetPlatform archList="all" binaryParser="com.xmos.cdt.core.XEBinaryParser;org.eclipse.cdt.core.GNU_ELF" id="com.xmos.cdt.core.platform.758545727" isAbstract="false" osList="linux,win32,macosx" superClass="com.xmos.cdt.core.platform"/>
<builder arguments="-f .makefile" id="com.xmos.cdt.builder.base.1807975194" keepEnvironmentInBuildfile="false" managedBuildOn="false" superClass="com.xmos.cdt.builder.base">
<outputEntries>
<entry flags="VALUE_WORKSPACE_PATH" kind="outputPath" name="bin"/>
</outputEntries>
</builder>
<tool id="com.xmos.cdt.xc.compiler.1603773068" name="com.xmos.cdt.xc.compiler" superClass="com.xmos.cdt.xc.compiler">
<option id="com.xmos.xc.compiler.option.include.paths.217515459" superClass="com.xmos.xc.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_logging/src}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_logging}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_logging/api}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_xassert/src}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_xassert}&quot;"/>
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</option>
<inputType id="com.xmos.cdt.xc.compiler.input.1097491589" name="XC" superClass="com.xmos.cdt.xc.compiler.input"/>
</tool>
<tool id="com.xmos.cdt.c.compiler.76882869" name="com.xmos.cdt.c.compiler" superClass="com.xmos.cdt.c.compiler">
<option id="com.xmos.c.compiler.option.include.paths.433678025" superClass="com.xmos.c.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_logging/src}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_logging}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_logging/api}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_xassert/src}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_xassert}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_xassert/api}&quot;"/>
</option>
<inputType id="com.xmos.cdt.c.compiler.input.c.1056834722" name="C" superClass="com.xmos.cdt.c.compiler.input.c"/>
</tool>
<tool id="com.xmos.cdt.cxx.compiler.1841285623" name="com.xmos.cdt.cxx.compiler" superClass="com.xmos.cdt.cxx.compiler">
<option id="com.xmos.cxx.compiler.option.include.paths.463620766" superClass="com.xmos.cxx.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_logging/src}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_logging}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_logging/api}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_xassert/src}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_xassert}&quot;"/>
<listOptionValue builtIn="false" value="&quot;${workspace_loc:/lib_xassert/api}&quot;"/>
</option>
<inputType id="com.xmos.cdt.cxx.compiler.input.cpp.1143236111" name="C++" superClass="com.xmos.cdt.cxx.compiler.input.cpp"/>
</tool>
</toolChain>
</folderInfo>
<sourceEntries>
<entry excluding=".build*" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="scannerConfiguration">
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
</storageModule>
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<project id="lib_src.null.1142937535" name="lib_src"/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
</cproject>

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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>lib_src</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>com.xmos.cdt.core.LegacyProjectCheckerBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.xmos.cdt.core.ProjectInfoSyncBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>com.xmos.cdt.core.ModulePathBuilder</name>
<arguments>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
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<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
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<nature>com.xmos.cdt.core.XdeProjectNature</nature>
</natures>
</projectDescription>

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*******************************
XMOS PUBLIC LICENCE: Version 1
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41
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// Copyright 2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _asrc_timestamp_interpolation_h_
#define _asrc_timestamp_interpolation_h_
#include "src.h"
#ifdef __XC__
#define UNSAFE unsafe
#else
#define UNSAFE
#endif
/**
* \addtogroup src_fifo_interp src_fifo_interp
*
* The public API for using Asynchronous FIFO.
* @{
*/
/**
* Function that interpolates a timestamp for a sample generated by the ASRC.
* Given a measured timestamp for the sample going into the ASRC, the asrc control
* structure, and the expected output frequency, this function returns a timestamp
* for when the last sample was produced by the ASRC.
*
* @param timestamp Value of the reference clock taken when the last sample
* fed into the ASRC was sampled.
*
* @param asrc_ctrl ASRC control block
*
* @param ideal_freq Expected base frequency to which the ASRC is operating;
* eg, 48000 or 44100
*/
int asrc_timestamp_interpolation(int timestamp, asrc_ctrl_t * UNSAFE asrc_ctrl, int ideal_freq);
/**@}*/ // END: addtogroup src_fifo_interp
#endif

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// Copyright 2023-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _asynchronous_fifo_h__
#define _asynchronous_fifo_h__
#include <stdint.h>
#include <xccompat.h>
#define FREQUENCY_RATIO_EXPONENT (32)
#ifdef __XC__
#define UNSAFE unsafe
#else
#define UNSAFE
#endif
/**
* \addtogroup src_fifo src_fifo
*
* The public API for using Asynchronous FIFO.
* @{
*/
/**
* Data structure that holds the status of an asynchronous FIFO
*/
typedef struct asynchronous_fifo_t {
// Updated on initialisation only
int32_t channel_count; /* Number of audio channels */
int32_t copy_mask; /* Number of audio channels */
int32_t max_fifo_depth; /* Length of buffer[] in channel_counts */
int32_t ideal_phase_error_ticks; /* Ideal ticks between samples */
int32_t Ki; /* Ki PID coefficient */
int32_t Kp; /* Kp PID coefficient */
// Updated on the producer side only
int skip_ctr; /* Set to indicate initialisation runs */
int32_t write_ptr; /* Write index in the buffer */
int64_t last_phase_error; /* previous error, used for proportional */
int64_t frequency_ratio; /* Current ratio of frequencies in 64.64 */
int32_t stop_producing; /* In case of overflow, stops producer until consumer restarts and requests a reset */
// Updated on the consumer side only
uint32_t read_ptr; /* Read index in the buffer */
// Set by producer, reset by consumer
uint32_t reset; /* Set to 1 if consumer wants a reset */
// Updated from both sides
uint32_t * UNSAFE timestamps; /* Timestamps of samples */
int32_t buffer[0]; /* Buffer of data */
} asynchronous_fifo_t;
/**
* Function that must be called to initialise the asynchronous FIFO.
* The ``state`` argument should be an int64_t array of
* ``ASYNCHRONOUS_FIFO_INT64_ELEMENTS`` elements that is cast to
* ``asynchronous_fifo_t*``.
*
* That pointer should also be used for all other operations, including operations
* both the consumer and producer sides.
*
* After initialising, you must initialise the PID by calling one of
* asynchronous_fifo_init_PID_fs_codes() or
* asynchronous_fifo_init_PID_raw()
*
* @param state Asynchronous FIFO to be initialised
*
* @param channel_count Number of audio channels
*
* @param max_fifo_depth Length of the FIFO, delay when stable will be max_fifo_depth/2
*/
void asynchronous_fifo_init(asynchronous_fifo_t * UNSAFE state,
int channel_count,
int max_fifo_depth);
/**
* Function that that initialises the PID of a FIFO. Either this function
* or asynchronous_fifo_init_PID_raw() should be called. This function
* uses frequency codes as defined in the ASRC for a quick default setup,
* the raw function allows full control
*
* @param state Asynchronous FIFO to be initialised
*
* @param fs_input Input FS ratio, used to pick appropriate Kp, and Ki.
* Must be a number less than 6.
*
* @param fs_output Input FS ratio, used to pick appropriate Kp, Ki,
* ideal phase. Must be a number less than 6.
*/
void asynchronous_fifo_init_PID_fs_codes(asynchronous_fifo_t * UNSAFE state,
int fs_input,
int fs_output);
/**
* Function that that initialises the PID of a FIFO. Either this function
* or asynchronous_fifo_init_PID_raw() should be called. This function
* uses frequency codes as defined in the ASRC for a quick default setup,
* the raw function allows full control.
*
* This function may be called at any time by the producer in order to alter the PID
* and midpoint settings. It does not reset the error; one of the
* asynchronous_fifo_init_reset_producer() or
* asynchronous_fifo_init_reset_consumer() functions should be called for that.
*
* @param state Asynchronous FIFO to be initialised
*
* @param Kp Proportional constant for the FIFO.
* This gets multiplied by the differential
* error measured in ticks (typically -2..2)
* and added to the ratio_error. A typical
* value is 30,000,000 - 60,000,000.
*
* @param Ki Integral constant for the FIFO.
* This gets multiplied by the phase error
* measured in ticks (typically -20,000 - 20,000)
* and added to the ratio_error.
* A typical value is 200 - 300.
*
* @param ticks_between_samples The number of ticks between samples is used to
* estimate the expected phase error halfway down
* the FIFO.
*/
void asynchronous_fifo_init_PID_raw(asynchronous_fifo_t * UNSAFE state,
int Kp,
int Ki,
int ticks_between_samples);
/**
* Function that that resets the FIFO from the producer side. Either this function should
* be called on the producing side, or ``asynchronous_fifo_reset_consumer``
* should be called on the consumer side. In both cases the whole FIFO will be reset back
*
* @param state Asynchronous FIFO to be initialised
*/
void asynchronous_fifo_reset_producer(asynchronous_fifo_t * UNSAFE state);
/**
* Function that that resets the FIFO from the consumer side. Either this function should
* be called on the consuming side, or asynchronous_fifo_reset_producer()
* should be called on the producer side. In both cases the whole FIFO will be reset back
*
* @param state Asynchronous FIFO to be initialised
*/
void asynchronous_fifo_reset_consumer(asynchronous_fifo_t * UNSAFE state);
/**
* Function that must be called to deinitalise the asynchronous FIFO
*
* @param state ASRC structure to be de-initialised
*/
void asynchronous_fifo_exit(asynchronous_fifo_t * UNSAFE state);
/**
* Function that provides the next samples to the asynchronous FIFO.
*
* This function and asynchronous_fifo_consumer_get() function both need a timestamp,
* which is the time that the last sample was input (this function) or
* output (asynchronous_fifo_consumer_get()). The asynchronous FIFO will hand the
* samples across from producer to consumer through an elastic queue, and run
* a PID algorithm to calculate the best way to equalise the input clock relative
* to the output clock. Therefore, the timestamps
* have to be measured on either the same clock or two very similar clocks.
* It is probably fine to use the reference clocks on two tiles, provided
* the tiles came out of reset at more or less the same time. Using the
* clocks from two different chips would require the two chips to share an
* oscillator, and for them to come out of reset simultaneously.
*
* @param state ASRC structure to push the sample into
*
* @param samples The sample values.
*
* @param n The number of samples
*
* @param timestamp The number of ticks when this sample was input.
*
* @param xscope_used Set to 1 if the PID values should be output over
* xscope. Used for debugging. This parameter is subject to be removed in future revisions.
*
* @returns The current estimate of the mismatch of input and output frequencies.
* This is represented as a 32-bit signed number. Zero means no mismatch,
* a value less than zero means that the producer is faster than the consumer,
* a value greater than zero means that the producer is slower than the consumer.
* The value should be scaled by 2**-32. That is, the current best
* approximation for consumer_speed/producer_speed is 1 + (return_value * 2**-32)
*
* The output is filtered and should be applied directly as a correction factor
* eg, multiplied into an ASRC ratio, or multiplied into a PLL timing.
*/
int32_t asynchronous_fifo_producer_put(asynchronous_fifo_t * UNSAFE state,
int32_t * UNSAFE samples,
int n,
int32_t timestamp,
int xscope_used);
/**
* Function that gets an output sample from the asynchronous FIFO
*
* @param state ASRC structure to read a sample out off.
*
* @param samples The array where the frame with output
* samples will be stored.
*
* @param timestamp A timestamp taken at the time that the
* last sample was output. See
* ``asynchronous_fifo_produce`` for requirements.
*/
void asynchronous_fifo_consumer_get(asynchronous_fifo_t * UNSAFE state,
int32_t * UNSAFE samples,
int32_t timestamp);
/**
* macro that calculates the number of int64_t to be allocated for the fifo
* for a FIFO of N elements and C channels
*/
#define ASYNCHRONOUS_FIFO_INT64_ELEMENTS(N, C) (sizeof(asynchronous_fifo_t)/sizeof(int64_t) + (N*(C+1))/2+1)
#endif
/**@}*/ // END: addtogroup src_fifo

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// Copyright 2016-2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _SRC_H_
#define _SRC_H_
#include "src_mrhf_ssrc.h"
#include "src_mrhf_asrc.h"
#include "src_ff3_ds3.h"
#include "src_ff3_os3.h"
#include "src_ff3v_fir.h"
#if (defined(__XS3A__)) // Only available for XS3 with VPU
#include "src_poly.h"
#endif // __XS3A__
#include <stdint.h>
#if defined(__cplusplus) || defined(__XC__)
extern "C" {
#endif
/** List of sample rate codes allowing the core SRC algorithms to use an index value */
typedef enum fs_code_t {
FS_CODE_44 = 0,
FS_CODE_48 = 1,
FS_CODE_88 = 2,
FS_CODE_96 = 3,
FS_CODE_176 = 4,
FS_CODE_192 = 5
} fs_code_t;
/** Flag to switch dither processing to 24b (from 32b) on or off */
typedef enum dither_flag_t {
OFF = 0,
ON = 1
} dither_flag_t;
/**
* \addtogroup src_ssrc src_ssrc
*
* The public API for using SSRC.
* @{
*/
/** initializes synchronous sample rate conversion instance.
* \param sr_in Nominal sample rate code of input stream
* \param sr_out Nominal sample rate code of output stream
* \param ssrc_ctrl Reference to array of SSRC control stuctures
* \param n_channels_per_instance Number of channels handled by this instance of SSRC
* \param n_in_samples Number of input samples per SSRC call
* \param dither_on_off Dither to 24b on/off
*/
void ssrc_init(const fs_code_t sr_in, const fs_code_t sr_out, ssrc_ctrl_t ssrc_ctrl[],
const unsigned n_channels_per_instance, const unsigned n_in_samples,
const dither_flag_t dither_on_off);
/** Perform synchronous sample rate conversion processing on block of input samples using previously initialized settings.
*
* \param in_buff Reference to input sample buffer array
* \param out_buff Reference to output sample buffer array
* \param ssrc_ctrl Reference to array of SSRC control stuctures
* \returns The number of output samples produced by the SRC operation
*/
unsigned ssrc_process(int in_buff[], int out_buff[], ssrc_ctrl_t ssrc_ctrl[]);
/**@}*/ // END: addtogroup src_ssrc
/**
* \addtogroup src_asrc src_asrc
*
* The public API for using ASRC.
* @{
*/
/** initializes asynchronous sample rate conversion instance.
*
* \param sr_in Nominal sample rate code of input stream
* \param sr_out Nominal sample rate code of output stream
* \param asrc_ctrl Reference to array of ASRC control structures
* \param n_channels_per_instance Number of channels handled by this instance of SSRC
* \param n_in_samples Number of input samples per SSRC call
* \param dither_on_off Dither to 24b on/off
* \returns The nominal sample rate ratio of in to out in Q4.60 format
*/
uint64_t asrc_init(const fs_code_t sr_in, const fs_code_t sr_out,
asrc_ctrl_t asrc_ctrl[], const unsigned n_channels_per_instance,
const unsigned n_in_samples, const dither_flag_t dither_on_off);
/** Perform asynchronous sample rate conversion processing on block of input samples using previously initialized settings.
*
* \param in_buff Reference to input sample buffer array
* \param out_buff Reference to output sample buffer array
* \param fs_ratio Fixed point ratio of in/out sample rates in Q4.60 format
* \param asrc_ctrl Reference to array of ASRC control structures
* \returns The number of output samples produced by the SRC operation.
*/
unsigned asrc_process(int in_buff[], int out_buff[], uint64_t fs_ratio,
asrc_ctrl_t asrc_ctrl[]);
/**@}*/ // END: addtogroup src_asrc
// To avoid C type definitions when including this file from assembler
#ifndef INCLUDE_FROM_ASM
/** Fixed factor of 3 return codes
*
* This type describes the possible error status states from calls to the DS3
* and OS3 API.
*/
typedef enum src_ff3_return_code_t
{
SRC_FF3_NO_ERROR = 0,
SRC_FF3_ERROR = 1
} src_ff3_return_code_t;
/** Downsample by 3 control structure */
typedef struct src_ds3_ctrl_t
{
int* in_data; //!< Pointer to input data (3 samples)
int* out_data; //!< Pointer to output data (1 sample)
int* delay_base; //!< Pointer to delay line base
unsigned int delay_len; //!< Total length of delay line
int* delay_pos; //!< Pointer to current position in delay line
int* delay_wrap; //!< Delay buffer wrap around address (for circular buffer simulation)
unsigned int delay_offset; //!< Delay line offset for second write (for circular buffer simulation)
unsigned int inner_loops; //!< Number of inner loop iterations
unsigned int num_coeffs; //!< Number of coefficients
int* coeffs; //!< Pointer to coefficients
} src_ds3_ctrl_t;
/** This function initializes the decimate by 3 function for a given instance
*
* \param src_ds3_ctrl DS3 control structure
* \returns SRC_FF3_NO_ERROR on success, SRC_FF3_ERROR on failure
*/
src_ff3_return_code_t src_ds3_init(src_ds3_ctrl_t* src_ds3_ctrl);
/** This function clears the decimate by 3 delay line for a given instance
*
* \param src_ds3_ctrl DS3 control structure
* \returns SRC_FF3_NO_ERROR on success, SRC_FF3_ERROR on failure
*/
src_ff3_return_code_t src_ds3_sync(src_ds3_ctrl_t* src_ds3_ctrl);
/** This function performs the decimation on three input samples and outputs one sample.
* The input and output buffers are pointed to by members of the src_ds3_ctrl structure
*
* \param src_ds3_ctrl DS3 control structure
* \returns SRC_FF3_NO_ERROR on success, SRC_FF3_ERROR on failure
*/
src_ff3_return_code_t src_ds3_proc(src_ds3_ctrl_t* src_ds3_ctrl);
/** Oversample by 3 control structure */
typedef struct src_os3_ctrl_t
{
int in_data; //!< Input data (to be updated every 3 output samples, i.e. when iPhase == 0)
int out_data; //!< Output data (1 sample)
int phase; //!< Current output phase (when reaching '0', a new input sample is required)
int* delay_base; //!< Pointer to delay line base
unsigned int delay_len; //!< Total length of delay line
int* delay_pos; //!< Pointer to current position in delay line
int* delay_wrap; //!< Delay buffer wrap around address (for circular buffer simulation)
unsigned int delay_offset; //!< Delay line offset for second write (for circular buffer simulation)
unsigned int inner_loops; //!< Number of inner loop iterations
unsigned int num_coeffs; //!< Number of coefficients
int* coeffs; //!< Pointer to coefficients
} src_os3_ctrl_t;
/** This function initializes the oversample by 3 function for a given instance
*
* \param src_os3_ctrl OS3 control structure
* \returns SRC_FF3_NO_ERROR on success, SRC_FF3_ERROR on failure
*/
src_ff3_return_code_t src_os3_init(src_os3_ctrl_t* src_os3_ctrl);
/** This function clears the oversample by 3 delay line for a given instance
*
* \param src_os3_ctrl OS3 control structure
* \returns SRC_FF3_NO_ERROR on success, SRC_FF3_ERROR on failure
*/
src_ff3_return_code_t src_os3_sync(src_os3_ctrl_t* src_os3_ctrl);
/** This function pushes a single input sample into the filter.
* It should be called three times for each FIROS3_proc call
*
* \param src_os3_ctrl OS3 control structure
* \returns SRC_FF3_NO_ERROR on success, SRC_FF3_ERROR on failure
*/
src_ff3_return_code_t src_os3_input(src_os3_ctrl_t* src_os3_ctrl);
/** This function performs the oversampling by 3 and outputs one sample.
* The input and output buffers are pointed to by members of the src_os3_ctrl structure
*
* \param src_os3_ctrl OS3 control structure
* \returns SRC_FF3_NO_ERROR on success, SRC_FF3_ERROR on failure
*/
src_ff3_return_code_t src_os3_proc(src_os3_ctrl_t* src_os3_ctrl);
#endif // INCLUDE_FROM_ASM
#if defined(__cplusplus) || defined(__XC__)
}
#endif
/** This function performs the first two iterations of the downsampling process
*
* \param sum Partially accumulated value returned during previous cycle
* \param data Data delay line
* \param coefs FIR filter coefficients
* \param sample The newest sample
* \returns Partially accumulated value, passed as ``sum`` parameter next cycle
*/
int64_t src_ds3_voice_add_sample(int64_t sum, int32_t data[],
const int32_t coefs[], int32_t sample);
/** This function performs the final iteration of the downsampling process
*
* \param sum Partially accumulated value returned during previous cycle
* \param data Data delay line
* \param coefs FIR filter coefficients
* \param sample The newest sample
* \returns The decimated sample
*/
int64_t src_ds3_voice_add_final_sample(int64_t sum, int32_t data[],
const int32_t coefs[], int32_t sample);
/** This function performs the initial iteration of the upsampling process
*
* \param data Data delay line
* \param coefs FIR filter coefficients
* \param sample The newest sample
* \returns A decimated sample
*/
int32_t src_us3_voice_input_sample(int32_t data[], const int32_t coefs[],
int32_t sample);
/** This function performs the final two iterations of the upsampling process
*
* \param data Data delay line
* \param coefs FIR filter coefficients
* \returns A decimated sample
*/
int32_t src_us3_voice_get_next_sample(int32_t data[], const int32_t coefs[]);
#endif // _SRC_H_

21
lib_src/lib_src/lib_build_info.cmake Normal file
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@@ -0,0 +1,21 @@
set(LIB_NAME lib_src)
set(LIB_VERSION 2.5.0)
set(LIB_DEPENDENT_MODULES "lib_logging(3.2.0)")
set(LIB_COMPILER_FLAGS -Wno-missing-braces -O3)
set(LIB_OPTIONAL_HEADERS src_conf.h)
set(LIB_INCLUDES api
src/fixed_factor_of_3
src/fixed_factor_of_3/ds3
src/fixed_factor_of_3/os3
src/fixed_factor_of_3_voice
src/multirate_hifi
src/multirate_hifi/asrc
src/multirate_hifi/ssrc
src/fixed_factor_vpu_voice)
XMOS_REGISTER_MODULE()

23
lib_src/lib_src/module_build_info Normal file
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@@ -0,0 +1,23 @@
VERSION = 2.5.0
DEPENDENT_MODULES = lib_logging(>=3.2.0)
MODULE_XCC_FLAGS = $(XCC_FLAGS) \
-Wno-missing-braces \
-O3
OPTIONAL_HEADERS += src_conf.h
EXPORT_INCLUDE_DIRS = api \
src/fixed_factor_of_3 \
src/fixed_factor_of_3/ds3 \
src/fixed_factor_of_3/os3 \
src/fixed_factor_of_3_voice \
src/multirate_hifi \
src/multirate_hifi/asrc \
src/multirate_hifi/ssrc \
src/fixed_factor_vpu_voice \
src/asrc_task
INCLUDE_DIRS = $(EXPORT_INCLUDE_DIRS)

18
lib_src/lib_src/src/asrc_timestamp_interpolation.c Normal file
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@@ -0,0 +1,18 @@
// Copyright 2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#include <stdint.h>
#include "asrc_timestamp_interpolation.h"
// TODO: replace TODO with BASE and 8/24 with division with MAX
// TODO: check with 88200 and other input frequencies
int asrc_timestamp_interpolation(int timestamp, asrc_ctrl_t *asrc_ctrl, int interpolation_ticks) {
// iTimeInt is an 8-bit number; fract a 32 bit number, with the two we make a 16-bit
// fraction that we multiply with and then shift down by 16 bits.
uint32_t fraction_away_from_final_ts = (((asrc_ctrl->iTimeInt - 128) << 8) |
((asrc_ctrl->uiTimeFract >> 24) & 0xff));
int32_t left_over_ticks = (fraction_away_from_final_ts * interpolation_ticks) >> 16;
return timestamp + left_over_ticks;
}

217
lib_src/lib_src/src/asynchronous_fifo.c Normal file
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@@ -0,0 +1,217 @@
// Copyright 2023-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#include <string.h>
#include "asynchronous_fifo.h"
#include <xcore/chanend.h>
#include <platform.h>
#include <xs1.h>
#include <print.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <xscope.h>
#include "src.h"
// TODO: Make fifo offset from N/2 a very small component in PID,
/**
* Function that resets the producing side of the ASRC; called on initialisation, and
* and called during reset by the producer after the consumer is known to have thrown
* in the towel
*/
static void asynchronous_fifo_init_producing_side(asynchronous_fifo_t *state) {
state->skip_ctr = state->max_fifo_depth / 2 + 2;
state->write_ptr = (state->read_ptr + state->max_fifo_depth/2) % state->max_fifo_depth;
state->last_phase_error = 0;
state->frequency_ratio = 0; // Assume perfect match
state->stop_producing = 0;
}
/**
* Function that resets the consuming side of the ASRC; called on initialisation, and
* and called during reset by the consumer before it notifies the producer that a reset
* is needed.
*/
static void asynchronous_fifo_reset_consumer_flags(asynchronous_fifo_t *state) {
state->reset = 0; // This has to be the last one
}
#define K_SHIFT 16
static int ticks_between_samples_1D[6] = {
2268,2083,1134,1042, 567, 521
};
static int Ki_2D[6][6] = {
{ 422, 422, 422, 422, 422, 422 },
{ 422, 422, 422, 422, 422, 422 },
{ 211, 211, 211, 211, 211, 211 },
{ 211, 211, 211, 211, 211, 211 },
{ 105, 105, 105, 105, 105, 105 },
{ 105, 105, 105, 105, 105, 105 }
};
static int Kp_2D[6][6] = {
{ 28147498, 28147498, 56294996, 56294996, 112589992, 112589992 },
{ 28147498, 28147498, 56294996, 56294996, 112589992, 112589992 },
{ 14073749, 14073749, 28147498, 28147498, 56294996, 56294996 },
{ 14073749, 14073749, 28147498, 28147498, 56294996, 56294996 },
{ 7036874, 7036874, 14073749, 14073749, 28147498, 28147498 },
{ 7036874, 7036874, 14073749, 14073749, 28147498, 28147498 }
};
void asynchronous_fifo_init_PID_fs_codes(asynchronous_fifo_t *state,
int fs_input, int fs_output) {
int max_fifo_depth = state->max_fifo_depth;
state->Kp = Kp_2D[fs_input][fs_output];
state->Ki = Ki_2D[fs_input][fs_output];
state->ideal_phase_error_ticks = ticks_between_samples_1D[fs_output] * (max_fifo_depth/2 + 1);
}
void asynchronous_fifo_init_PID_raw(asynchronous_fifo_t *state,
int Kp, int Ki, int ticks_between_samples) {
int max_fifo_depth = state->max_fifo_depth;
state->Kp = Kp;
state->Ki = Ki;
state->ideal_phase_error_ticks = ticks_between_samples * (max_fifo_depth/2 + 1);
}
void asynchronous_fifo_init(asynchronous_fifo_t *state, int channel_count,
int max_fifo_depth) {
state->max_fifo_depth = max_fifo_depth;
state->timestamps = (uint32_t *)state->buffer + max_fifo_depth * channel_count;
state->channel_count = channel_count;
state->copy_mask = (1 << (4*channel_count)) - 1;
// First initialise shared variables, or those that shouldn't reset on a RESET.
state->read_ptr = 0;
// Now clear the buffer.
memset(state->buffer, 0, channel_count * max_fifo_depth * sizeof(int));
// Finally initialise those parts that are reset on a RESET
asynchronous_fifo_init_producing_side(state); // uses read_ptr
asynchronous_fifo_reset_consumer_flags(state);
}
void asynchronous_fifo_exit(asynchronous_fifo_t *state) {
}
int async_resets = 0;
void asynchronous_fifo_reset_producer(asynchronous_fifo_t *state) {
state->stop_producing = 1;
}
void asynchronous_fifo_reset_consumer(asynchronous_fifo_t *state) {
state->reset = 1;
}
int32_t asynchronous_fifo_producer_put(asynchronous_fifo_t *state, int32_t *samples,
int n,
int32_t timestamp,
int xscope_used) {
int read_ptr = state->read_ptr;
int write_ptr = state->write_ptr;
int max_fifo_depth = state->max_fifo_depth;
int channel_count = state->channel_count;
int copy_mask = state->copy_mask;
int len = (write_ptr - read_ptr + max_fifo_depth) % max_fifo_depth;
if (state->reset) {
async_resets++;
asynchronous_fifo_init_producing_side(state); // uses read_ptr
asynchronous_fifo_reset_consumer_flags(state); // Last step - clears reset
} else if (len >= max_fifo_depth - 2 - n) {
state->stop_producing = 1;
} else if (!state->stop_producing && n) {
for(int j = 0; j < n; j++) {
#ifdef __XS2A__
memcpy(state->buffer + write_ptr * channel_count, samples, channel_count * sizeof(int));
(void)copy_mask; // Remove unused var warning
#else
register int32_t *ptr asm("r11") = samples;
asm("vldr %0[0]" :: "r" (ptr));
asm("vstrpv %0[0], %1" :: "r" (state->buffer + write_ptr * channel_count), "r" (copy_mask));
#endif
samples += channel_count;
write_ptr = (write_ptr + 1);
if (write_ptr >= max_fifo_depth) {
write_ptr = 0;
}
}
/* Difference between timestamp recorded by consumer and current timestamp */
state->write_ptr = write_ptr;
int32_t phase_error = state->timestamps[write_ptr] - timestamp;
/* Ideal phase error is the middle of the fifo measured in ticks */
phase_error += state->ideal_phase_error_ticks;
/* Don't try and use timestamps that haven't been recorded yet! */
if (state->skip_ctr != 0) {
state->skip_ctr--;
} else {
// Now that we have a phase error, calculate the proportional error
// and use that and the integral error to correct the ASRC factor
int32_t diff_error = phase_error - state->last_phase_error;
state->frequency_ratio +=
(diff_error * (int64_t) (state->Kp / n)) + // TODO: make this lookup table
(phase_error * (int64_t) state->Ki);
if (xscope_used) {
#if defined(ASYNC_FIFO_XSCOPE_INSTRUMENTATION)
xscope_int(1, phase_error);
xscope_int(2, diff_error);
#endif
}
}
state->last_phase_error = phase_error;
}
if (xscope_used) {
#if defined(ASYNC_FIFO_XSCOPE_INSTRUMENTATION)
xscope_int(3, len);
xscope_int(4, state->frequency_ratio >> K_SHIFT);
#endif
}
return (state->frequency_ratio + (1<<(K_SHIFT-1))) >> K_SHIFT;
}
/**
* Function that implements the consumer interface. Control communication
* happens through two variables: reset and sample_data_valid. These shall
* only be set as the last action, as they signify to the production side
* that the datastructure can now be read on that side.
*
* Note that the samples are filled in regardless of whether the FIFO is
* operating or not; the consumer will repeatedly get the same sample if
* the producer fails. The producer side is reset exactly once on reset.
*/
void asynchronous_fifo_consumer_get(asynchronous_fifo_t *state, int32_t *samples, int32_t timestamp) {
int read_ptr = state->read_ptr;
int write_ptr = state->write_ptr;
int max_fifo_depth = state->max_fifo_depth;
int channel_count = state->channel_count;
int copy_mask = state->copy_mask;
int len = (write_ptr - read_ptr + max_fifo_depth) % max_fifo_depth;
#ifdef __XS2A__
memcpy(samples, state->buffer + read_ptr * channel_count, channel_count * sizeof(int));
(void)copy_mask; // Remove unused var warning
#else
register int32_t *ptr asm("r11") = state->buffer + read_ptr * channel_count;
asm("vldr %0[0]" :: "r" (ptr));
asm("vstrpv %0[0], %1" :: "r" (samples), "r" (copy_mask));
#endif
if (state->reset) {
return;
}
if (len > 2) {
// TODO: use IF not %
read_ptr = (read_ptr + 1) % state->max_fifo_depth;
state->read_ptr = read_ptr;
state->timestamps[read_ptr] = timestamp;
} else {
state->reset = 1; // The rest must happen in the other thread
}
}

145
lib_src/lib_src/src/fixed_factor_of_3/ds3/FilterData/firds3_144.dat Normal file
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lib_src/lib_src/src/fixed_factor_of_3/ds3/FilterData/firds3_144.sfp Normal file
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lib_src/lib_src/src/fixed_factor_of_3/ds3/FilterData/firds3_b_144.dat Normal file
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lib_src/lib_src/src/fixed_factor_of_3/ds3/FilterData/firds3_b_144.sfp Normal file
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142
lib_src/lib_src/src/fixed_factor_of_3/ds3/src_ff3_ds3.c Normal file
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// Copyright 2016-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
// ===========================================================================
// ===========================================================================
//
// FIRDS3 functions implementation file
//
// ===========================================================================
// ===========================================================================
// ===========================================================================
//
// Includes
//
// ===========================================================================
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
#include "src.h"
#include "src_ff3_ds3.h"
#include "src_ff3_fir_inner_loop_asm.h"
// ===========================================================================
//
// Defines
//
// ===========================================================================
// State init value
#define SRC_FF3_DS3_STATE_INIT 0
// ===========================================================================
//
// Variables
//
// ===========================================================================
int src_ds3_coeffs[SRC_FF3_DS3_N_COEFS] = {
#include SRC_FF3_DS3_COEFS_FILE
};
// ===========================================================================
//
// Local Functions prototypes
//
// ===========================================================================
// ===========================================================================
//
// Functions implementations
//
// ===========================================================================
src_ff3_return_code_t src_ds3_init(src_ds3_ctrl_t* src_ds3_ctrl)
{
// Check that delay line base has been set
if (src_ds3_ctrl->delay_base == 0) {
return SRC_FF3_ERROR;
}
// Setup from FIRDS2 descriptor
src_ds3_ctrl->delay_len = SRC_FF3_DS3_N_COEFS<<1; // Double length for circular buffer simulation
src_ds3_ctrl->delay_wrap = src_ds3_ctrl->delay_base + SRC_FF3_DS3_N_COEFS;
src_ds3_ctrl->delay_offset = SRC_FF3_DS3_N_COEFS;
src_ds3_ctrl->inner_loops = (SRC_FF3_DS3_N_COEFS>>1) / SRC_FF3_N_LOOPS_PER_ASM; // Right shift to 2 x 32bits read for coefs per inner loop
src_ds3_ctrl->num_coeffs = SRC_FF3_DS3_N_COEFS;
src_ds3_ctrl->coeffs = src_ds3_coeffs;
// Sync the FIRDS3
if (src_ds3_sync(src_ds3_ctrl) != SRC_FF3_NO_ERROR) {
return SRC_FF3_ERROR;
}
return SRC_FF3_NO_ERROR;
}
src_ff3_return_code_t src_ds3_sync(src_ds3_ctrl_t* src_ds3_ctrl)
{
// Set delay line index back to base
src_ds3_ctrl->delay_pos = src_ds3_ctrl->delay_base;
// Clear delay line
for (unsigned int ui = 0; ui < src_ds3_ctrl->delay_len; ui++) {
src_ds3_ctrl->delay_base[ui] = SRC_FF3_DS3_STATE_INIT;
}
return SRC_FF3_NO_ERROR;
}
src_ff3_return_code_t src_ds3_proc(src_ds3_ctrl_t* src_ds3_ctrl)
{
int* data;
int* coeffs;
int data0;
__int64_t accumulator;
// Get three new data samples to delay line (double write for circular buffer simulation)
data0 = *src_ds3_ctrl->in_data;
*src_ds3_ctrl->delay_pos = data0;
*(src_ds3_ctrl->delay_pos + src_ds3_ctrl->delay_offset) = data0;
data0 = *(src_ds3_ctrl->in_data + 1);
*(src_ds3_ctrl->delay_pos + 1) = data0;
*(src_ds3_ctrl->delay_pos + src_ds3_ctrl->delay_offset + 1) = data0;
data0 = *(src_ds3_ctrl->in_data + 2);
*(src_ds3_ctrl->delay_pos + 2) = data0;
*(src_ds3_ctrl->delay_pos + src_ds3_ctrl->delay_offset + 2) = data0;
// Step delay with circular simulation (will also rewrite to control structure for next round)
// Note as delay line length is a multiple of 3 (because filter coefficients length is a multiple of 3)
// we only have to do the wrap around check after having written 3 input samples
src_ds3_ctrl->delay_pos += 3;
if (src_ds3_ctrl->delay_pos >= src_ds3_ctrl->delay_wrap) {
src_ds3_ctrl->delay_pos = src_ds3_ctrl->delay_base;
}
// Clear accumulator and set access pointers
data = src_ds3_ctrl->delay_pos;
coeffs = src_ds3_ctrl->coeffs;
accumulator = 0;
if ((unsigned)data & 0b0100) {
src_ff3_fir_inner_loop_asm_odd(data, coeffs, &data0, src_ds3_ctrl->inner_loops);
} else {
src_ff3_fir_inner_loop_asm(data, coeffs, &data0, src_ds3_ctrl->inner_loops);
}
*src_ds3_ctrl->out_data = data0;
return SRC_FF3_NO_ERROR;
}

22
lib_src/lib_src/src/fixed_factor_of_3/ds3/src_ff3_ds3.h Normal file
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// Copyright 2016-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _SRC_FF3_DS3_H_
#define _SRC_FF3_DS3_H_
#ifdef __XC__
extern "C" {
#endif
#define SRC_FF3_DS3_N_COEFS 144 // Number of coefficients must be a multiple of 6
/* Filters with "_b_" in their filenames have higher attenuation at
* Nyquist (> 60dB compared with 20dB ) but with an earlier cutoff.
*/
#define SRC_FF3_DS3_COEFS_FILE "FilterData/firds3_b_144.dat"
//#define SRC_FF3_DS3_COEFS_FILE "FilterData/firds3_144.dat"
#ifdef __XC__
}
#endif
#endif // _SRC_FF3_DS3_H_

145
lib_src/lib_src/src/fixed_factor_of_3/os3/FilterData/firos3_144.dat Normal file
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lib_src/lib_src/src/fixed_factor_of_3/os3/FilterData/firos3_144.sfp Normal file
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lib_src/lib_src/src/fixed_factor_of_3/os3/FilterData/firos3_b_144.dat Normal file
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lib_src/lib_src/src/fixed_factor_of_3/os3/FilterData/firos3_b_144.sfp Normal file
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135
lib_src/lib_src/src/fixed_factor_of_3/os3/src_ff3_os3.c Normal file
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// Copyright 2016-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
// ===========================================================================
// ===========================================================================
//
// FIROS3 functions implementation file
//
// ===========================================================================
// ===========================================================================
// ===========================================================================
//
// Includes
//
// ===========================================================================
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
#include "src.h"
#include "src_ff3_os3.h"
#include "src_ff3_fir_inner_loop_asm.h"
// ===========================================================================
//
// Defines
//
// ===========================================================================
// State init value
#define SRC_OS3_STATE_INIT 0
// ===========================================================================
//
// Variables
//
// ===========================================================================
int src_os3_coeffs[SRC_FF3_OS3_N_COEFS] = {
#include SRC_FF3_OS3_COEFS_FILE
};
// ===========================================================================
//
// Functions implementations
//
// ===========================================================================
src_ff3_return_code_t src_os3_init(src_os3_ctrl_t* src_os3_ctrl)
{
// Check that delay line base has been set
if (src_os3_ctrl->delay_base == 0) {
return SRC_FF3_ERROR;
}
// Setup from FIROS2 descriptor
src_os3_ctrl->delay_len = (SRC_FF3_OS3_N_COEFS/SRC_FF3_OS3_N_PHASES)<<1; // Double length for circular buffer simulation. x3 over-sampler, so only 1/3rd of coefs length needed
src_os3_ctrl->delay_wrap = src_os3_ctrl->delay_base + (SRC_FF3_OS3_N_COEFS/SRC_FF3_OS3_N_PHASES);
src_os3_ctrl->delay_offset = (SRC_FF3_OS3_N_COEFS/SRC_FF3_OS3_N_PHASES);
src_os3_ctrl->inner_loops = ((SRC_FF3_OS3_N_COEFS/SRC_FF3_OS3_N_PHASES)>>1) / SRC_FF3_N_LOOPS_PER_ASM; // Right shift due to 2 x 32bits read for coefs per inner loop and x3 over-sampler, so only 1/3rd of coefs length needed
src_os3_ctrl->num_coeffs = SRC_FF3_OS3_N_COEFS;
src_os3_ctrl->coeffs = src_os3_coeffs;
// Sync the FIROS3
if (src_os3_sync(src_os3_ctrl) != SRC_FF3_NO_ERROR) {
return SRC_FF3_ERROR;
}
return SRC_FF3_NO_ERROR;
}
src_ff3_return_code_t src_os3_sync(src_os3_ctrl_t* src_os3_ctrl)
{
// Set delay line index back to base
src_os3_ctrl->delay_pos = src_os3_ctrl->delay_base;
// Clear delay line
for (unsigned int ui = 0; ui < src_os3_ctrl->delay_len; ui++) {
src_os3_ctrl->delay_base[ui] = SRC_OS3_STATE_INIT;
}
// Set phase to '0' to indicate that a new input sample is needed
src_os3_ctrl->phase = 0;
return SRC_FF3_NO_ERROR;
}
src_ff3_return_code_t src_os3_input(src_os3_ctrl_t* src_os3_ctrl)
{
// Write new input sample from control structure to delay line
// at both positions for circular buffer simulation
*src_os3_ctrl->delay_pos = src_os3_ctrl->in_data;
*(src_os3_ctrl->delay_pos + src_os3_ctrl->delay_offset) = src_os3_ctrl->in_data;
// Step delay index with circular buffer simulation
src_os3_ctrl->delay_pos += 1;
if (src_os3_ctrl->delay_pos >= src_os3_ctrl->delay_wrap) {
src_os3_ctrl->delay_pos = src_os3_ctrl->delay_base;
}
return SRC_FF3_NO_ERROR;
}
src_ff3_return_code_t src_os3_proc(src_os3_ctrl_t* src_os3_ctrl)
{
int* data;
int* coeffs;
int data0;
__int64_t accumulator;
// Clear accumulator and set data/coefs access pointers
data = src_os3_ctrl->delay_pos;
coeffs = src_os3_ctrl->coeffs + src_os3_ctrl->phase;
accumulator = 0;
if ((unsigned)data & 0b0100) {
src_ff3_fir_inner_loop_asm_odd(data, coeffs, &data0, src_os3_ctrl->inner_loops);
} else {
src_ff3_fir_inner_loop_asm(data, coeffs, &data0, src_os3_ctrl->inner_loops);
}
// Write output
src_os3_ctrl->out_data = data0;
// Step phase
src_os3_ctrl->phase += (SRC_FF3_OS3_N_COEFS/SRC_FF3_OS3_N_PHASES);
if (src_os3_ctrl->phase == SRC_FF3_OS3_N_COEFS) {
src_os3_ctrl->phase = 0;
}
return SRC_FF3_NO_ERROR;
}

23
lib_src/lib_src/src/fixed_factor_of_3/os3/src_ff3_os3.h Normal file
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@@ -0,0 +1,23 @@
// Copyright 2016-2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _SRC_FF3_OS3_H_
#define _SRC_FF3_OS3_H_
#ifdef __XC__
extern "C" {
#endif
#define SRC_FF3_OS3_N_COEFS 144 // Number of coefficients must be a multiple of 6
#define SRC_FF3_OS3_N_PHASES 3 // Number of output phases (3 as OS3 over-sample by 3)
/* Filters with "_b_" in their filenames have higher attenuation at
* 8kHz (> 60dB compared with 20dB ) but with an earlier cutoff.
*/
// #define SRC_FF3_OS3_COEFS_FILE "FilterData/firos3_b_144.dat"
#define SRC_FF3_OS3_COEFS_FILE "FilterData/firos3_144.dat"
#ifdef __XC__
}
#endif
#endif // _SRC_FF3_OS3_H_

290
lib_src/lib_src/src/fixed_factor_of_3/src_ff3_fir_inner_loop_asm.S Normal file
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// Copyright 2016-2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
.section .dp.data,"awd",@progbits
.text
.cc_top src_ff3_fir_inner_loop_asm.function
.globl src_ff3_fir_inner_loop_asm
.align 8
.type src_ff3_fir_inner_loop_asm,@function
src_ff3_fir_inner_loop_asm:
#define piData_p r0
#define piCoefs_p r1
#define iDataRet_p r2
#define step r2
#define counter r3
#define iCoef0 r4
#define iCoef1 r5
#define iData0 r6
#define iData1 r7
#define Acc0_l r8
#define Acc0_h r9
//In 32b words
#define stack_size 8
.issue_mode dual
//Push registers
DUALENTSP_lu6 stack_size
std r4, r5, sp[0]
std r6, r7, sp[1]
std r8, r9, sp[2]
//push return value pointers onto stack. Frees up r2
stw iDataRet_p, sp[6]
//Constant for adding onto stuff. Gets updated later
ldc step, 0x60
//Initilise MACC regsiters to zero
{ldc Acc0_h, 0; ldc Acc0_l, 0}
bf counter, done
main_loop:
sub counter, counter, 1
ldd iData0, iData1, piData_p[0]
ldd iCoef0, iCoef1, piCoefs_p[0]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[1]
ldd iCoef0, iCoef1, piCoefs_p[1]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[2]
ldd iCoef0, iCoef1, piCoefs_p[2]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[3]
ldd iCoef0, iCoef1, piCoefs_p[3]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[4]
ldd iCoef0, iCoef1, piCoefs_p[4]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[5]
ldd iCoef0, iCoef1, piCoefs_p[5]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[6]
ldd iCoef0, iCoef1, piCoefs_p[6]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[7]
ldd iCoef0, iCoef1, piCoefs_p[7]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[8]
ldd iCoef0, iCoef1, piCoefs_p[8]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[9]
ldd iCoef0, iCoef1, piCoefs_p[9]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[10]
ldd iCoef0, iCoef1, piCoefs_p[10]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[11]
ldd iCoef0, iCoef1, piCoefs_p[11]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
//Decrement loop counter and increment pointers and branch if still running
{add piData_p, piData_p, step; add piCoefs_p, piCoefs_p, step}
bt counter, main_loop
done:
//pop return value pointer from stack so we can use it to write back
//Write back the two return values
{ldw iDataRet_p, sp[6]; ldc counter, 31} //Reuse counter (r3)
lsats Acc0_h, Acc0_l, r3 //Saturate first
lextract iData0, Acc0_h, Acc0_l, counter, 32 //Extract
stw iData0, iDataRet_p[0]
//Pop registers
ldd r4, r5, sp[0]
ldd r6, r7, sp[1]
ldd r8, r9, sp[2]
retsp stack_size
.atmp:
.size src_ff3_fir_inner_loop_asm, .atmp-src_ff3_fir_inner_loop_asm
.align 8
.cc_bottom src_ff3_fir_inner_loop_asm.function
.set src_ff3_fir_inner_loop_asm.nstackwords, stack_size
.globl src_ff3_fir_inner_loop_asm.nstackwords
.set src_ff3_fir_inner_loop_asm.maxcores, 1
.globl src_ff3_fir_inner_loop_asm.maxcores
.set src_ff3_fir_inner_loop_asm.maxtimers,0
.globl src_ff3_fir_inner_loop_asm.maxtimers
.set src_ff3_fir_inner_loop_asm.maxchanends,0
.globl src_ff3_fir_inner_loop_asm.maxchanends
.section .dp.data,"awd",@progbits
.text
.cc_top src_ff3_fir_inner_loop_asm_odd.function
.globl src_ff3_fir_inner_loop_asm_odd
.align 8
.type src_ff3_fir_inner_loop_asm_odd,@function
src_ff3_fir_inner_loop_asm_odd:
#define piData_p r0
#define piCoefs_p r1
#define iDataRet_p r2
#define step r2
#define counter r3
#define iCoef0 r4
#define iCoef1 r5
#define iData0 r6
#define iData1 r7
#define Acc0_l r8
#define Acc0_h r9
//In 32b words
#define stack_size 8
.issue_mode dual
//Push registers
DUALENTSP_lu6 stack_size
std r4, r5, sp[0]
std r6, r7, sp[1]
std r8, r9, sp[2]
//push return value pointers onto stack. Frees up r2
stw iDataRet_p, sp[6]
//Initilise MACC regsiters to zero
{ldc Acc0_h, 0; ldc Acc0_l, 0}
ldc step, 0x60
bf counter, done
main_loop_odd:
{sub counter, counter, 1; sub step, step, 8} //Sub gets loaded with 0x60 at end of loop
//We actually want 0x58 so this is good
//Constant for adding onto stuff. Gets updated later
{ldw iData0, piData_p[0]; add piData_p, piData_p, 4} //Now 64b aligned
ldd iCoef1, iCoef0, piCoefs_p[0]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[0]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[1]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[1]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[2]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[2]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[3]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[3]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[4]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[4]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[5]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[5]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[6]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[6]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[7]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[7]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[8]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[8]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[9]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[9]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[10]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[10]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[11]
maccs Acc0_h, Acc0_l, iData0, iCoef0
add piData_p, piData_p, step
{ldw iData1, piData_p[0]; add piData_p, piData_p, 4} //0x4 + 0x58 + 0x4 = 0x60)
maccs Acc0_h, Acc0_l, iData1, iCoef1
//Increment pointers and branch if still running
ldc step, 0x60
{bt counter, main_loop_odd; add piCoefs_p, piCoefs_p, step}
done_odd:
//pop return value pointer from stack so we can use it to write back
{ldw iDataRet_p, sp[6]; ldc counter, 31} //Reuse counter (r3)
//Write back the return value
lsats Acc0_h, Acc0_l, r3 //Saturate first
lextract iData0, Acc0_h, Acc0_l, counter, 32 //Extract
stw iData0, iDataRet_p[0]
//Pop registers
ldd r4, r5, sp[0]
ldd r6, r7, sp[1]
ldd r8, r9, sp[2]
retsp stack_size
.atmp_odd:
.size src_ff3_fir_inner_loop_asm_odd, .atmp-src_ff3_fir_inner_loop_asm_odd
.align 8
.cc_bottom src_ff3_fir_inner_loop_asm_odd.function
.set src_ff3_fir_inner_loop_asm_odd.nstackwords, stack_size
.globl src_ff3_fir_inner_loop_asm_odd.nstackwords
.set src_ff3_fir_inner_loop_asm_odd.maxcores, 1
.globl src_ff3_fir_inner_loop_asm_odd.maxcores
.set src_ff3_fir_inner_loop_asm_odd.maxtimers,0
.globl src_ff3_fir_inner_loop_asm_odd.maxtimers
.set src_ff3_fir_inner_loop_asm_odd.maxchanends,0
.globl src_ff3_fir_inner_loop_asm_odd.maxchanends

12
lib_src/lib_src/src/fixed_factor_of_3/src_ff3_fir_inner_loop_asm.h Normal file
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// Copyright 2016-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _SRC_FF3_FIR_INNER_LOOP_ASM_H_
#define _SRC_FF3_FIR_INNER_LOOP_ASM_H_
#define SRC_FF3_N_LOOPS_PER_ASM 12
void src_ff3_fir_inner_loop_asm(int *piData, int *piCoefs, int iData[], int count);
void src_ff3_fir_inner_loop_asm_odd(int *piData, int *piCoefs, int iData[], int count);
#endif // _SRC_FF3_FIR_INNER_LOOP_ASM_H_

94
lib_src/lib_src/src/fixed_factor_of_3_voice/ds3_voice/src_ff3v_ds3_voice.S Normal file
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// Copyright 2016-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
.section .dp.data,"awd",@progbits
.text
#define STACKWORDS 4
#define c0 r4
#define c1 r5
#define d0 r6
#define s r11
.cc_top src_ds3_voice_add_sample.function
.globl src_ds3_voice_add_sample
.align 4
.type src_ds3_voice_add_sample,@function
src_ds3_voice_add_sample://(int64_t sum, int32_t data[], int32_t coefs[], int32_t sample);
.issue_mode dual
DUALENTSP_lu6 STACKWORDS
std r4, r5, sp[0]
std r6, r7, sp[1]
ldw s, sp[STACKWORDS+1]
bl src_ff3v_fir_impl
ldd r4, r5, sp[0]
ldd r6, r7, sp[1]
retsp STACKWORDS
.src_ds3_voice_add_sample_tmp:
.size src_ds3_voice_add_sample, .src_ds3_voice_add_sample_tmp-src_ds3_voice_add_sample
.align 4
.cc_bottom src_ds3_voice_add_sample.function
.set src_ds3_voice_add_sample.nstackwords, STACKWORDS
.globl src_ds3_voice_add_sample.nstackwords
.set src_ds3_voice_add_sample.maxcores,1
.globl src_ds3_voice_add_sample.maxcores
.set src_ds3_voice_add_sample.maxtimers,0
.globl src_ds3_voice_add_sample.maxtimers
.set src_ds3_voice_add_sample.maxchanends,0
.globl src_ds3_voice_add_sample.maxchanends
.cc_top src_ds3_voice_add_final_sample.function
.globl src_ds3_voice_add_final_sample
.align 4
.type src_ds3_voice_add_final_sample,@function
src_ds3_voice_add_final_sample://(int64_t sum, int32_t data[], int32_t coefs[], int32_t sample);
.issue_mode dual
DUALENTSP_lu6 STACKWORDS
std r4, r5, sp[0]
std r6, r7, sp[1]
ldw s, sp[STACKWORDS+1]
bl src_ff3v_fir_impl
{ldc d0, 31; nop}
lextract r0, r1, r0, d0, 32
ldaw s, cp[src_ff3v_fir_comp_ds]
ldw s, s[0]
{ldc c0, 0; ldc c1, 0}
maccs c0, c1, r0, s
ldaw s, cp[src_ff3v_fir_comp_q_ds]
ldw s, s[0]
lsats c0, c1, s
lextract r0, c0, c1, s, 32
ldd r4, r5, sp[0]
ldd r6, r7, sp[1]
{retsp STACKWORDS; ldc r1, 0}
.src_ds3_voice_add_final_sample_tmp:
.size src_ds3_voice_add_final_sample, .src_ds3_voice_add_final_sample_tmp-src_ds3_voice_add_final_sample
.align 4
.cc_bottom src_ds3_voice_add_final_sample.function
.set src_ds3_voice_add_final_sample.nstackwords, STACKWORDS
.globl src_ds3_voice_add_final_sample.nstackwords
.set src_ds3_voice_add_final_sample.maxcores,1
.globl src_ds3_voice_add_final_sample.maxcores
.set src_ds3_voice_add_final_sample.maxtimers,0
.globl src_ds3_voice_add_final_sample.maxtimers
.set src_ds3_voice_add_final_sample.maxchanends,0
.globl src_ds3_voice_add_final_sample.maxchanends

63
lib_src/lib_src/src/fixed_factor_of_3_voice/src_ff3v_fir.S Normal file
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// Copyright 2017-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
.section .dp.data,"awd",@progbits
.text
#define sum_l r0
#define sum_h r1
#define data r2
#define coefs r3
#define c0 r4
#define c1 r5
#define d0 r6
#define d1 r7
#define s r11
#define EVEN_STEP(N) \
ldd c1, c0, coefs[N];\
maccs sum_h, sum_l, c0, s;\
ldd d1, d0, data[N];\
maccs sum_h, sum_l, c1, d0;\
std d0, s, data[N];
#define ODD_STEP(N) \
ldd c1, c0, coefs[N];\
maccs sum_h, sum_l, c0, d1;\
ldd s, d0, data[N];\
maccs sum_h, sum_l, c1, d0;\
std d0, d1, data[N];
.cc_top src_ff3v_fir_impl.function
.globl src_ff3v_fir_impl
.align 8
.type src_ff3v_fir_impl,@function
.issue_mode dual
src_ff3v_fir_impl:
EVEN_STEP(0);
ODD_STEP(1);
EVEN_STEP(2);
ODD_STEP(3);
EVEN_STEP(4);
ODD_STEP(5);
EVEN_STEP(6);
ODD_STEP(7);
EVEN_STEP(8);
ODD_STEP(9);
EVEN_STEP(10);
ODD_STEP(11);
{retsp 0; nop}
.src_ff3v_fir_impl_tmp:
.size src_ff3v_fir_impl, .src_ff3v_fir_impl_tmp-src_ff3v_fir_impl
.align 4
.cc_bottom src_ff3v_fir_impl.function
.set src_ff3v_fir_impl.nstackwords, 0
.globl src_ff3v_fir_impl.nstackwords
.set src_ff3v_fir_impl.maxcores,1
.globl src_ff3v_fir_impl.maxcores
.set src_ff3v_fir_impl.maxtimers,0
.globl src_ff3v_fir_impl.maxtimers
.set src_ff3v_fir_impl.maxchanends,0
.globl src_ff3v_fir_impl.maxchanends

33
lib_src/lib_src/src/fixed_factor_of_3_voice/src_ff3v_fir.h Normal file
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// Copyright 2016-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
//
// This file is generated using src_ff3v_fir_generator.py
//
// Do not modify it directly, changes may be overwritten!
//
#ifndef _SRC_FF3V_FIR_H_
#define _SRC_FF3V_FIR_H_
#include <stdint.h>
#define SRC_FF3V_FIR_NUM_PHASES (3)
#define SRC_FF3V_FIR_TAPS_PER_PHASE (24)
extern const unsigned src_ff3v_fir_comp_q_ds;
extern const int32_t src_ff3v_fir_comp_ds;
extern const unsigned src_ff3v_fir_comp_q_us;
extern const int32_t src_ff3v_fir_comp_us;
extern int32_t src_ff3v_fir_coefs_debug[SRC_FF3V_FIR_NUM_PHASES * SRC_FF3V_FIR_TAPS_PER_PHASE];
#if defined(__XC__)
extern const int32_t (*src_ff3v_fir_coefs_xc)[SRC_FF3V_FIR_TAPS_PER_PHASE];
#define src_ff3v_fir_coefs src_ff3v_fir_coefs_xc
#else
extern const int32_t (*src_ff3v_fir_coefs_c)[SRC_FF3V_FIR_TAPS_PER_PHASE];
#define src_ff3v_fir_coefs src_ff3v_fir_coefs_c
#endif
#endif // _SRC_FF3V_FIR_H_

67
lib_src/lib_src/src/fixed_factor_of_3_voice/src_ff3v_fir.xc Normal file
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// Copyright 2016-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
//
// This file is generated using src_ff3v_fir_generator.py
//
// Do not modify it directly, changes may be overwritten!
//
#include "src_ff3v_fir.h"
#include <stdint.h>
/** Used for FIR compensation for decimation*/
const unsigned src_ff3v_fir_comp_q_ds = 29;
/** Used for FIR compensation for decimation*/
const int32_t src_ff3v_fir_comp_ds = 1112549167;
/** Used for FIR compensation for upsampling*/
const unsigned src_ff3v_fir_comp_q_us = 27;
/** Used for FIR compensation for upsampling*/
const int32_t src_ff3v_fir_comp_us = 834411870;
/** Used for self testing src_ds3_voice and src_us3_voice functionality */
int32_t src_ff3v_fir_coefs_debug[SRC_FF3V_FIR_NUM_PHASES * SRC_FF3V_FIR_TAPS_PER_PHASE] = {
1005142, 1367390, 29412, -4146838, -10154637, -14619962,
-13776186, -6744830, 2692812, 8121360, 5508436, -2814524,
-9285443, -7351357, 2193307, 10930750, 9953155, -1338213,
-13227624, -13683020, -123797, 16201217, 19008511, 2582573,
-20205295, -27041699, -6837031, 26249516, 40760231, 15085431,
-37763299, -71330011, -37235961, 74585089, 219245690, 320542055,
320542055, 219245690, 74585089, -37235961, -71330011, -37763299,
15085431, 40760231, 26249516, -6837031, -27041699, -20205295,
2582573, 19008511, 16201217, -123797, -13683020, -13227624,
-1338213, 9953155, 10930750, 2193307, -7351357, -9285443,
-2814524, 5508436, 8121360, 2692812, -6744830, -13776186,
-14619962, -10154637, -4146838, 29412, 1367390, 1005142,
};
/** Coefficients for use with src_ds3_voice and src_us3_voice functions */
static const int32_t [[aligned(8)]] src_ff3v_fir_coefs_i[SRC_FF3V_FIR_NUM_PHASES][SRC_FF3V_FIR_TAPS_PER_PHASE] = {
{
29412, -14619962, 2692812, -2814524, 2193307, -1338213,
-123797, 2582573, -6837031, 15085431, -37235961, 320542055,
74585089, -37763299, 26249516, -20205295, 16201217, -13227624,
10930750, -9285443, 8121360, -13776186, -4146838, 1005142,
},
{
1367390, -10154637, -6744830, 5508436, -7351357, 9953155,
-13683020, 19008511, -27041699, 40760231, -71330011, 219245690,
219245690, -71330011, 40760231, -27041699, 19008511, -13683020,
9953155, -7351357, 5508436, -6744830, -10154637, 1367390,
},
{
1005142, -4146838, -13776186, 8121360, -9285443, 10930750,
-13227624, 16201217, -20205295, 26249516, -37763299, 74585089,
320542055, -37235961, 15085431, -6837031, 2582573, -123797,
-1338213, 2193307, -2814524, 2692812, -14619962, 29412,
},
};
unsafe {
const int32_t (* unsafe src_ff3v_fir_coefs_c)[SRC_FF3V_FIR_TAPS_PER_PHASE] = src_ff3v_fir_coefs_i;
}
const int32_t (*src_ff3v_fir_coefs_xc)[SRC_FF3V_FIR_TAPS_PER_PHASE] = src_ff3v_fir_coefs_i;

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lib_src/lib_src/src/fixed_factor_of_3_voice/src_ff3v_fir_generator.py Normal file
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#!/usr/bin/env python
# Copyright 2016-2021 XMOS LIMITED.
# This Software is subject to the terms of the XMOS Public Licence: Version 1.
import os.path
import numpy as np
from scipy import signal
import matplotlib.pyplot as plt
def plot_response(fs, w, h, title):
plt.figure()
plt.plot(0.5*fs*w/np.pi, 20*np.log10(np.abs(h)))
plt.xlim(0, 0.5*fs)
plt.grid(True)
plt.xlabel('Frequency (Hz)')
plt.ylabel('Gain (dB)')
plt.title(title)
plt.show()
def plot_response_passband(fs, w, h, title):
plt.figure()
plt.plot(0.5*fs*w/np.pi, 20*np.log10(np.abs(h)))
plt.ylim(-1, 1)
plt.xlim(0, 0.25*fs)
plt.grid(True)
plt.xlabel('Frequency (Hz)')
plt.ylabel('Gain (dB)')
plt.title(title)
plt.show()
def generate_header_file(num_taps_per_phase, num_phases):
header_template = """\
// Copyright (c) 2016-2021, XMOS Ltd, All rights reserved
//
// This file is generated using src_ff3v_fir_generator.py
//
// Do not modify it directly, changes may be overwritten!
//
#ifndef _SRC_FF3V_FIR_H_
#define _SRC_FF3V_FIR_H_
#include <stdint.h>
#define SRC_FF3V_FIR_NUM_PHASES (%(phases)s)
#define SRC_FF3V_FIR_TAPS_PER_PHASE (%(taps_per_phase)s)
extern const unsigned src_ff3v_fir_comp_q_ds;
extern const int32_t src_ff3v_fir_comp_ds;
extern const unsigned src_ff3v_fir_comp_q_us;
extern const int32_t src_ff3v_fir_comp_us;
extern int32_t src_ff3v_fir_coefs_debug[SRC_FF3V_FIR_NUM_PHASES * SRC_FF3V_FIR_TAPS_PER_PHASE];
#if defined(__XC__)
extern const int32_t (*src_ff3v_fir_coefs_xc)[SRC_FF3V_FIR_TAPS_PER_PHASE];
#define src_ff3v_fir_coefs src_ff3v_fir_coefs_xc
#else
extern const int32_t (*src_ff3v_fir_coefs_c)[SRC_FF3V_FIR_TAPS_PER_PHASE];
#define src_ff3v_fir_coefs src_ff3v_fir_coefs_c
#endif
#endif // _SRC_FF3V_FIR_H_
"""
header_path = os.path.join(os.path.dirname(os.path.realpath(__file__)),
'src_ff3v_fir.h')
with open(header_path, "w") as header_file:
header_file.writelines(header_template % {'taps_per_phase':num_taps_per_phase,
'phases':num_phases})
def generate_xc_file(q_ds, q_us, comp_ds, comp_us, taps):
xc_template = """\
// Copyright (c) 2016-2021, XMOS Ltd, All rights reserved
//
// This file is generated using src_ff3v_fir_generator.py
//
// Do not modify it directly, changes may be overwritten!
//
#include "src_ff3v_fir.h"
#include <stdint.h>
/** Used for FIR compensation for decimation*/
const unsigned src_ff3v_fir_comp_q_ds = %(comp_q_ds)s;
/** Used for FIR compensation for decimation*/
const int32_t src_ff3v_fir_comp_ds = %(comp_ds)s;
/** Used for FIR compensation for upsampling*/
const unsigned src_ff3v_fir_comp_q_us = %(comp_q_us)s;
/** Used for FIR compensation for upsampling*/
const int32_t src_ff3v_fir_comp_us = %(comp_us)s;
/** Used for self testing src_ds3_voice and src_us3_voice functionality */
int32_t src_ff3v_fir_coefs_debug[SRC_FF3V_FIR_NUM_PHASES * SRC_FF3V_FIR_TAPS_PER_PHASE] = {
%(coefs_debug)s
};
/** Coefficients for use with src_ds3_voice and src_us3_voice functions */
static const int32_t [[aligned(8)]] src_ff3v_fir_coefs_i[SRC_FF3V_FIR_NUM_PHASES][SRC_FF3V_FIR_TAPS_PER_PHASE] = {
%(coefs)s};
unsafe {
const int32_t (* unsafe src_ff3v_fir_coefs_c)[SRC_FF3V_FIR_TAPS_PER_PHASE] = src_ff3v_fir_coefs_i;
}
const int32_t (*src_ff3v_fir_coefs_xc)[SRC_FF3V_FIR_TAPS_PER_PHASE] = src_ff3v_fir_coefs_i;
"""
coefs_debug = ''
i = 1
for c in taps:
coefs_debug += (' ' + str(int(c*(2**31 - 1))).rjust(12) + ',')
if ((i % 6) == 0):
coefs_debug += '\n'
i+=1
coefs = ''
for step in range(num_phases-1, -1, -1):
i = 1
coefs += ' {\n '
for j in range(step, len(taps), num_phases):
coefs += ' ' + str(int(taps[j]*(2**31 - 1))).rjust(12) + ','
if ((i % 6) == 0):
coefs += '\n '
i+=1
coefs += '},\n'
xc_path = os.path.join(os.path.dirname(os.path.realpath(__file__)),
'src_ff3v_fir.xc')
with open(xc_path, "w") as xc_file:
xc_file.writelines(xc_template % {'comp_q_ds':str(q_ds),
'comp_ds':str(comp_ds),
'comp_q_us':str(q_us),
'comp_us':str(comp_us),
'coefs_debug':coefs_debug,
'coefs':coefs})
# Low-pass filter design parameters
fs = 48000.0 # Sample rate, Hz
num_phases = 3
num_taps_per_phase = 2*12
taps = signal.remez((num_phases*num_taps_per_phase), [0, 7300, 8700, 0.5*fs], [1, 0], [.008, 1], Hz=fs)
w, h = signal.freqz(taps)
pass_band_atten = sum(abs(taps))
upsampling_atten = num_phases
taps = taps / pass_band_atten # Guarantee no overflow
# generate the compensation factors
q_ds = 30 - int(np.log2(pass_band_atten) + 0.5)
q_us = 30 - int(np.log2(pass_band_atten * upsampling_atten) + 0.5)
comp_ds = int(((2**q_ds)-1) * pass_band_atten)
comp_us = int(((2**q_us)-1) * pass_band_atten * upsampling_atten)
if __name__ == "__main__":
# plot_response(fs, w, h, "Low-pass Filter")
# plot_response_passband(fs, w, h, "Low-pass Filter")
generate_header_file(num_taps_per_phase, num_phases)
generate_xc_file(q_ds, q_us, comp_ds, comp_us, taps)

137
lib_src/lib_src/src/fixed_factor_of_3_voice/us3_voice/src_ff3v_us3_voice.S Normal file
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// Copyright 2017-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
.section .dp.data,"awd",@progbits
.text
#define STACKWORDS 4
#define sum_l r0
#define sum_h r1
#define data r2
#define coefs r3
#define c0 r4
#define c1 r5
#define d0 r6
#define d1 r7
#define s r11
#define TWO_TAPS_NO_STORE(N) \
ldd c1, c0, coefs[N];\
ldd d1, d0, data[N];\
maccs sum_h, sum_l, c0, d0;\
maccs sum_h, sum_l, c1, d1;
.cc_top src_us3_voice_input_sample.function
.globl src_us3_voice_input_sample
.align 4
.type src_us3_voice_input_sample,@function
src_us3_voice_input_sample://(int32_t data[], int32_t coefs[], int32_t sample);
.issue_mode dual
DUALENTSP_lu6 STACKWORDS
std r4, r5, sp[0]
std r6, r7, sp[1]
// TODO: fix this by renaming the registers
mov s, r2
{mov r2, r0; mov r3, r1}
{ldc r0, 0; ldc r1, 0}
bl src_ff3v_fir_impl
{ldc d0, 31; nop}
lextract r0, r1, r0, d0, 32
ldaw s, cp[src_ff3v_fir_comp_us]
ldw s, s[0]
{ldc c0, 0; ldc c1, 0}
maccs c0, c1, r0, s
ldaw s, cp[src_ff3v_fir_comp_q_us]
ldw s, s[0]
lsats c0, c1, s
lextract r0, c0, c1, s, 32
ldd r4, r5, sp[0]
ldd r6, r7, sp[1]
retsp STACKWORDS
.src_us3_voice_input_sample_tmp:
.size src_us3_voice_input_sample, .src_us3_voice_input_sample_tmp-src_us3_voice_input_sample
.align 4
.cc_bottom src_us3_voice_input_sample.function
.set src_us3_voice_input_sample.nstackwords, STACKWORDS
.globl src_us3_voice_input_sample.nstackwords
.set src_us3_voice_input_sample.maxcores,1
.globl src_us3_voice_input_sample.maxcores
.set src_us3_voice_input_sample.maxtimers,0
.globl src_us3_voice_input_sample.maxtimers
.set src_us3_voice_input_sample.maxchanends,0
.globl src_us3_voice_input_sample.maxchanends
.cc_top src_us3_voice_get_next_sample.function
.globl src_us3_voice_get_next_sample
.align 4
.type src_us3_voice_get_next_sample,@function
src_us3_voice_get_next_sample://(int32_t data[], int32_t coefs[], int32_t sample);
.issue_mode dual
DUALENTSP_lu6 STACKWORDS
std r4, r5, sp[0]
std r6, r7, sp[1]
// TODO: fix this by renaming the registers
{mov r2, r0; mov r3, r1}
{ldc r0, 0; ldc r1, 0}
TWO_TAPS_NO_STORE(0)
TWO_TAPS_NO_STORE(1)
TWO_TAPS_NO_STORE(2)
TWO_TAPS_NO_STORE(3)
TWO_TAPS_NO_STORE(4)
TWO_TAPS_NO_STORE(5)
TWO_TAPS_NO_STORE(6)
TWO_TAPS_NO_STORE(7)
TWO_TAPS_NO_STORE(8)
TWO_TAPS_NO_STORE(9)
TWO_TAPS_NO_STORE(10)
TWO_TAPS_NO_STORE(11)
{ldc d0, 31; nop}
lextract r0, r1, r0, d0, 32
ldaw s, cp[src_ff3v_fir_comp_us]
ldw s, s[0]
{ldc c0, 0; ldc c1, 0}
maccs c0, c1, r0, s
ldaw s, cp[src_ff3v_fir_comp_q_us]
ldw s, s[0]
lsats c0, c1, s
lextract r0, c0, c1, s, 32
ldd r4, r5, sp[0]
ldd r6, r7, sp[1]
retsp STACKWORDS
.src_us3_voice_get_next_sample_tmp:
.size src_us3_voice_get_next_sample, .src_us3_voice_get_next_sample_tmp-src_us3_voice_get_next_sample
.align 4
.cc_bottom src_us3_voice_get_next_sample.function
.set src_us3_voice_get_next_sample.nstackwords, STACKWORDS
.globl src_us3_voice_get_next_sample.nstackwords
.set src_us3_voice_get_next_sample.maxcores,1
.globl src_us3_voice_get_next_sample.maxcores
.set src_us3_voice_get_next_sample.maxtimers,0
.globl src_us3_voice_get_next_sample.maxtimers
.set src_us3_voice_get_next_sample.maxchanends,0
.globl src_us3_voice_get_next_sample.maxchanends

66
lib_src/lib_src/src/fixed_factor_vpu_voice/asm/conv_s32_24t.S Normal file
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// Copyright 2023-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#define FUNCTION_NAME conv_s32_24t
#define NSTACKWORDS (8)
#define STACK_VEC_TMP (NSTACKWORDS - 8)
#define state r0
#define coef r1
#define buff r2
#define _32 r3
.text
.issue_mode dual
.globl FUNCTION_NAME;
.type FUNCTION_NAME,@function
.align 16
.cc_top FUNCTION_NAME.function,FUNCTION_NAME
FUNCTION_NAME: // (int32_t * state, int32_t * coef)
dualentsp NSTACKWORDS
#if (defined(__XS3A__)) // Only available for XS3 with VPU
// r4 - r10 are not used here
// Setting up the vpu and some constants
{ ldaw buff, sp[STACK_VEC_TMP] ; ldc r11, 0 }
{ ldc _32, 32 ; vsetc r11 }
{ vclrdr ; mov r11, state }
// Do convolution
{ ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ ; vlmaccr coef[0] }
// vR [0 - 2] has 3 macc results, store them
{ ; vstr buff[0] }
#undef state
#define out r0
#undef coef
#define tmp0 r1
#undef _32
#define tmp1 r3
// Load all the results and add them together
ldd out, tmp1, buff[0]
{ add out, out, tmp1 ; ldw tmp0, buff[2] }
{ add out, out, tmp0 ; }
#endif // Only available for XS3 with VPU
retsp NSTACKWORDS
.cc_bottom FUNCTION_NAME.function;
.set FUNCTION_NAME.nstackwords,NSTACKWORDS; .global FUNCTION_NAME.nstackwords;
.set FUNCTION_NAME.maxcores,1; .global FUNCTION_NAME.maxcores;
.set FUNCTION_NAME.maxtimers,0; .global FUNCTION_NAME.maxtimers;
.set FUNCTION_NAME.maxchanends,0; .global FUNCTION_NAME.maxchanends;
#undef FUNCTION_NAME

71
lib_src/lib_src/src/fixed_factor_vpu_voice/asm/conv_s32_32t.S Normal file
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// Copyright 2023-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#define FUNCTION_NAME conv_s32_32t
#define NSTACKWORDS (8)
#define STACK_VEC_TMP (NSTACKWORDS - 8)
#define state r0
#define coef r1
#define buff r2
#define _32 r3
.text
.issue_mode dual
.globl FUNCTION_NAME;
.type FUNCTION_NAME,@function
.align 16
.cc_top FUNCTION_NAME.function,FUNCTION_NAME
FUNCTION_NAME: // (int32_t * state, int32_t * coef)
dualentsp NSTACKWORDS
#if (defined(__XS3A__)) // Only available for XS3 with VPU
// r4 - r10 are not used here
// Setting up the vpu and some constants
{ ldaw buff, sp[STACK_VEC_TMP] ; ldc r11, 0 }
{ ldc _32, 32 ; vsetc r11 }
{ vclrdr ; mov r11, state }
// Do convolution
{ ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ ; vlmaccr coef[0] }
// vR [0 - 3] has 4 macc results, store them
{ ; vstr buff[0] }
#undef state
#define out r0
#undef coef
#define tmp0 r1
#undef _32
#define tmp1 r3
// Load all the results and add them together
ldd out, tmp1, buff[0]
{ add out, out, tmp1 ; ldw tmp0, buff[2] }
{ add out, out, tmp0 ; ldw tmp1, buff[3] }
{ add out, out, tmp1 ; }
#endif // Only available for XS3 with VPU
retsp NSTACKWORDS
.cc_bottom FUNCTION_NAME.function;
.set FUNCTION_NAME.nstackwords,NSTACKWORDS; .global FUNCTION_NAME.nstackwords;
.set FUNCTION_NAME.maxcores,1; .global FUNCTION_NAME.maxcores;
.set FUNCTION_NAME.maxtimers,0; .global FUNCTION_NAME.maxtimers;
.set FUNCTION_NAME.maxchanends,0; .global FUNCTION_NAME.maxchanends;
#undef FUNCTION_NAME

88
lib_src/lib_src/src/fixed_factor_vpu_voice/asm/fir_s32_24t.S Normal file
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// Copyright 2023-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#define FUNCTION_NAME fir_s32_24t
#define NSTACKWORDS (1 + 8)
#define STACK_VEC_TMP (NSTACKWORDS - 8)
#define state r0
#define coef r1
#define new_samp r2
#define indx r3
#define _32 r4
.text
.issue_mode dual
.globl FUNCTION_NAME;
.type FUNCTION_NAME,@function
.align 16
.cc_top FUNCTION_NAME.function,FUNCTION_NAME
FUNCTION_NAME: // (int32_t * state, int32_t * coef, int32_t new_samp)
dualentsp NSTACKWORDS
#if (defined(__XS3A__)) // Only available for XS3 with VPU
// r5 - r10 are not used here
// Setting up the vpu and a poiter to the state[15]
{ ldc r11, 0 ; stw r4, sp[0] }
{ ldc indx, 15 ; vsetc r11 }
{ ldc _32, 32 ; }
ldaw r11, state[indx] // r11 -> st[15 - 23]
// It's possible to undef "state" and reuse r0 for "_32" to reduce stack but it does not bring much value
#undef indx
#define buff r3
// It will shift the whole array with just 3 vldr + 3 vstr
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[16 - 24] // vR has st[15 - 23]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[7 - 15] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[8 - 16] // vR has st[7 - 15]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[-1 - 7] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[0 - 8] // vR has st[-1 - 7]
{ ; vstr buff[0] } // buff has vR
// Bring r11 back to state[0], clear the vector unit
{ add r11, r11, 4 ; vclrdr } // r11 -> st[0]
{ ldaw buff, sp[STACK_VEC_TMP] ; stw new_samp, state[0] } // buff -> sp[10] // put new_samp in state[0]
// Do convolution
{ ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ ; vlmaccr coef[0] }
// vR [0 - 2] has 3 macc results, store them
{ ; vstr buff[0] }
#undef state
#define out r0
#undef coef
#define tmp0 r1
#undef new_samp
#define tmp1 r2
// Load all the results and add them together
ldd out, tmp1, buff[0]
{ add out, out, tmp1 ; ldw tmp0, buff[2] }
{ add out, out, tmp0 ; ldw r4, sp[0] }
#endif // Only available for XS3 with VPU
retsp NSTACKWORDS
.cc_bottom FUNCTION_NAME.function;
.set FUNCTION_NAME.nstackwords,NSTACKWORDS; .global FUNCTION_NAME.nstackwords;
.set FUNCTION_NAME.maxcores,1; .global FUNCTION_NAME.maxcores;
.set FUNCTION_NAME.maxtimers,0; .global FUNCTION_NAME.maxtimers;
.set FUNCTION_NAME.maxchanends,0; .global FUNCTION_NAME.maxchanends;
#undef FUNCTION_NAME

96
lib_src/lib_src/src/fixed_factor_vpu_voice/asm/fir_s32_32t.S Normal file
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// Copyright 2023-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#define FUNCTION_NAME fir_s32_32t
#define NSTACKWORDS (1 + 8)
#define STACK_VEC_TMP (NSTACKWORDS - 8)
#define state r0
#define coef r1
#define new_samp r2
#define indx r3
#define _32 r4
.text
.issue_mode dual
.globl FUNCTION_NAME;
.type FUNCTION_NAME,@function
.align 16
.cc_top FUNCTION_NAME.function,FUNCTION_NAME
FUNCTION_NAME: // (int32_t * state, int32_t * coef, int32_t new_samp)
dualentsp NSTACKWORDS
#if (defined(__XS3A__)) // Only available for XS3 with VPU
// r5 - r10 are not used here
// Setting up the vpu and a poiter to the state[23]
{ ldc r11, 0 ; stw r4, sp[0] }
{ ldc indx, 23 ; vsetc r11 }
{ ldc _32, 32 ; }
ldaw r11, state[indx] // r11 -> st[23 - 31]
// It's possible to undef "state" and reuse r0 for "_32" to reduce stack but it does not bring much value
#undef indx
#define buff r3
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[24 - 32] // vR has st[23 - 31]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[15 - 23] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[16 - 24] // vR has st[15 - 23]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[7 - 15] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[8 - 16] // vR has st[7 - 15]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[-1 - 7] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[0 - 8] // vR has st[-1 - 7]
{ ; vstr buff[0] } // buff has vR
// Bring r11 back to state[0], clear the vector unit
{ add r11, r11, 4 ; vclrdr } // r11 -> st[0]
{ ldaw buff, sp[STACK_VEC_TMP] ; stw new_samp, state[0] } // buff -> sp[10] // put new_samp in state[0]
// Do convolution
{ ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ ; vlmaccr coef[0] }
// vR [0 - 3] has 4 macc results, store them
{ ; vstr buff[0] }
#undef state
#define out r0
#undef coef
#define tmp0 r1
#undef new_samp
#define tmp1 r2
// Load all the results and add them together
ldd out, tmp1, buff[0]
{ add out, out, tmp1 ; ldw tmp0, buff[2] }
{ add out, out, tmp0 ; ldw tmp1, buff[3] }
{ add out, out, tmp1 ; ldw r4, sp[0] }
#endif // Only available for XS3 with VPU
retsp NSTACKWORDS
.cc_bottom FUNCTION_NAME.function;
.set FUNCTION_NAME.nstackwords,NSTACKWORDS; .global FUNCTION_NAME.nstackwords;
.set FUNCTION_NAME.maxcores,1; .global FUNCTION_NAME.maxcores;
.set FUNCTION_NAME.maxtimers,0; .global FUNCTION_NAME.maxtimers;
.set FUNCTION_NAME.maxchanends,0; .global FUNCTION_NAME.maxchanends;
#undef FUNCTION_NAME

109
lib_src/lib_src/src/fixed_factor_vpu_voice/asm/fir_s32_48t.S Normal file
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// Copyright 2023-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#define FUNCTION_NAME fir_s32_48t
#define NSTACKWORDS (1 + 8)
#define STACK_VEC_TMP (NSTACKWORDS - 8)
#define state r0
#define coef r1
#define new_samp r2
#define indx r3
#define _32 r4
.text
.issue_mode dual
.globl FUNCTION_NAME;
.type FUNCTION_NAME,@function
.align 16
.cc_top FUNCTION_NAME.function,FUNCTION_NAME
FUNCTION_NAME: // (int32_t * state, int32_t * coef, int32_t new_samp)
dualentsp NSTACKWORDS
#if (defined(__XS3A__)) // Only available for XS3 with VPU
// r5 - r10 are not used here
// Setting up the vpu and a poiter to the state[39]
{ ldc r11, 0 ; stw r4, sp[0] }
{ ldc indx, 39 ; vsetc r11 }
{ ldc _32, 32 ; }
ldaw r11, state[indx] // r11 -> st[39 - 47]
// It's possible to undef "state" and reuse r0 for "_32" to reduce stack but it does not bring much value
#undef indx
#define buff r3
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[40 - 48] // vR has st[39 - 47]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[31 - 39] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[32 - 40] // vR has st[31 - 39]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[23 - 31] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[24 - 32] // vR has st[23 - 31]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[15 - 23] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[16 - 24] // vR has st[15 - 23]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[7 - 15] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[8 - 16] // vR has st[7 - 15]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[-1 - 7] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[0 - 8] // vR has st[-1 - 7]
{ ; vstr buff[0] } // buff has vR
// Bring r11 back to state[0], clear the vector unit
{ add r11, r11, 4 ; vclrdr } // r11 -> st[0]
{ ldaw buff, sp[STACK_VEC_TMP] ; stw new_samp, state[0] } // buff -> sp[10] // put new_samp in state[0]
// Do convolution
{ ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ add r11, r11, _32 ; vlmaccr coef[0] }
{ add coef, coef, _32 ; vldc r11[0] }
{ ; vlmaccr coef[0] }
// vR [0 - 5] has 6 macc results, store them
{ ; vstr buff[0] }
#undef state
#define out r0
#undef coef
#define tmp0 r1
#undef new_samp
#define tmp1 r2
// Load all the results and add them together
ldd out, tmp1, buff[0]
{ add out, out, tmp1 ; ldw tmp0, buff[2] }
{ add out, out, tmp0 ; ldw tmp1, buff[3] }
{ add out, out, tmp1 ; ldw tmp0, buff[4] }
{ add out, out, tmp0 ; ldw tmp1, buff[5] }
{ add out, out, tmp1 ; ldw r4, sp[0] }
#endif // Only available for XS3 with VPU
retsp NSTACKWORDS
.cc_bottom FUNCTION_NAME.function;
.set FUNCTION_NAME.nstackwords,NSTACKWORDS; .global FUNCTION_NAME.nstackwords;
.set FUNCTION_NAME.maxcores,1; .global FUNCTION_NAME.maxcores;
.set FUNCTION_NAME.maxtimers,0; .global FUNCTION_NAME.maxtimers;
.set FUNCTION_NAME.maxchanends,0; .global FUNCTION_NAME.maxchanends;
#undef FUNCTION_NAME

65
lib_src/lib_src/src/fixed_factor_vpu_voice/asm/push_s32_48t.S Normal file
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// Copyright 2023-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#define FUNCTION_NAME push_s32_48t
#define NSTACKWORDS (0)
#define state r0
#define new_samp r1
#define indx r2
#define _32 r3
.text
.issue_mode dual
.globl FUNCTION_NAME;
.type FUNCTION_NAME,@function
.align 16
.cc_top FUNCTION_NAME.function,FUNCTION_NAME
FUNCTION_NAME: // (int32_t * state, int32_t new_samp)
dualentsp NSTACKWORDS
#if (defined(__XS3A__)) // Only available for XS3 with VPU
// r4 - r10 are not used here
// Setting up the vpu and a poiter to the state[39]
{ ldc _32, 32 ; ldc r11, 0 }
{ ldc indx, 39 ; vsetc r11 }
{ ldaw r11, state[indx] ; } // r11 -> st[39 - 47]
#undef indx
#define buff r2
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[40 - 48] // vR has st[39 - 47]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[31 - 39] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[32 - 40] // vR has st[31 - 39]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[23 - 31] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[24 - 32] // vR has st[23 - 31]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[15 - 23] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[16 - 24] // vR has st[15 - 23]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[7 - 15] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[8 - 16] // vR has st[7 - 15]
{ sub r11, r11, _32 ; vstr buff[0] } // r11 -> st[-1 - 7] // buff has vR
{ add buff, r11, 4 ; vldr r11[0] } // buff -> st[0 - 8] // vR has st[-1 - 7]
{ ; vstr buff[0] } // buff has vR
// put new_samp in state[0]
{ ; stw new_samp, state[0] }
#endif // Only available for XS3 with VPU
retsp NSTACKWORDS
.cc_bottom FUNCTION_NAME.function;
.set FUNCTION_NAME.nstackwords,NSTACKWORDS; .global FUNCTION_NAME.nstackwords;
.set FUNCTION_NAME.maxcores,1; .global FUNCTION_NAME.maxcores;
.set FUNCTION_NAME.maxtimers,0; .global FUNCTION_NAME.maxtimers;
.set FUNCTION_NAME.maxchanends,0; .global FUNCTION_NAME.maxchanends;
#undef FUNCTION_NAME

59
lib_src/lib_src/src/fixed_factor_vpu_voice/src_ff3_fir_coefs.c Normal file
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@@ -0,0 +1,59 @@
// Copyright 2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
/*********************************/
/* AUTOGENERATED. DO NOT MODIFY! */
/*********************************/
// Use src_ff3_fir_gen.py script to regenare this file
// python src_ff3_fir_gen.py -gc True -ntp 32 -np 3
#include "src_ff3_fir_coefs.h"
#include <stdint.h>
/** q31 coefficients to use for debugging ff3 sample rate conversion */
const int32_t ALIGNMENT(8) src_ff3_fir_coefs_debug[SRC_FF3_FIR_NUM_PHASES * SRC_FF3_FIR_TAPS_PER_PHASE] = {
-132660, -391256, -272653, 294018, 790734, 513772,
-561508, -1423266, -881735, 972885, 2366363, 1416412,
-1572615, -3711773, -2165391, 2413069, 5568888, 3186277,
-3557131, -8071663, -4551171, 5083569, 11392367, 6355363,
-7097804, -15768801, -8734511, 9753621, 21559523, 11899941,
-13298806, -29362449, -16216509, 18178957, 40294588, 22394094,
-25305013, -56753765, -32043220, 36887788, 85009440, 49769829,
-60002604, -148154004, -96041427, 135812786, 454448559, 683203534,
683203534, 454448559, 135812786, -96041427, -148154004, -60002604,
49769829, 85009440, 36887788, -32043220, -56753765, -25305013,
22394094, 40294588, 18178957, -16216509, -29362449, -13298806,
11899941, 21559523, 9753621, -8734511, -15768801, -7097804,
6355363, 11392367, 5083569, -4551171, -8071663, -3557131,
3186277, 5568888, 2413069, -2165391, -3711773, -1572615,
1416412, 2366363, 972885, -881735, -1423266, -561508,
513772, 790734, 294018, -272653, -391256, -132660,
};
/** q30 coefficients to use for the ff3 48 - 16 kHz polyphase FIR filtering */
const int32_t ALIGNMENT(8) src_ff3_fir_coefs[SRC_FF3_FIR_NUM_PHASES][SRC_FF3_FIR_TAPS_PER_PHASE] = {
{
-136326, 256886, -440867, 708206, -1082695, 1593138,
-2275585, 3177682, -4367255, 5949971, -8108254, 11197047,
-16021610, 24884914, -48020712, 341601760, 67906392, -30001302,
18443894, -12652507, 9089479, -6649403, 4876810, -3548902,
2541785, -1778566, 1206534, -786307, 486442, -280754,
147009, -66330,},
{
-195628, 395367, -711633, 1183181, -1855886, 2784444,
-4035831, 5696184, -7884400, 10779762, -14681225, 20147294,
-28376882, 42504720, -74077000, 227224272, 227224272, -74077000,
42504720, -28376882, 20147294, -14681225, 10779762, -7884400,
5696184, -4035831, 2784444, -1855886, 1183181, -711633,
395367, -195628,},
{
-66330, 147009, -280754, 486442, -786307, 1206534,
-1778566, 2541785, -3548902, 4876810, -6649403, 9089479,
-12652507, 18443894, -30001302, 67906392, 341601760, -48020712,
24884914, -16021610, 11197047, -8108254, 5949971, -4367255,
3177682, -2275585, 1593138, -1082695, 708206, -440867,
256886, -136326,},
};

34
lib_src/lib_src/src/fixed_factor_vpu_voice/src_ff3_fir_coefs.h Normal file
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@@ -0,0 +1,34 @@
// Copyright 2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
/*********************************/
/* AUTOGENERATED. DO NOT MODIFY! */
/*********************************/
// Use src_ff3_fir_gen.py script to regenare this file
// python src_ff3_fir_gen.py -gc True -ntp 32 -np 3
#ifndef _SRC_FF3_COEFS_H_
#define _SRC_FF3_COEFS_H_
#include <stdint.h>
#ifndef ALIGNMENT
# ifdef __xcore__
# define ALIGNMENT(N) __attribute__((aligned (N)))
# else
# define ALIGNMENT(N)
# endif
#endif
#define SRC_FF3_FIR_NUM_PHASES (3)
#define SRC_FF3_FIR_TAPS_PER_PHASE (32)
/** q31 coefficients to use for debugging ff3 sample rate conversion */
extern const int32_t src_ff3_fir_coefs_debug[SRC_FF3_FIR_NUM_PHASES * SRC_FF3_FIR_TAPS_PER_PHASE];
/** q30 coefficients to use for the ff3 48 - 16 kHz polyphase FIR filtering */
extern const int32_t src_ff3_fir_coefs[SRC_FF3_FIR_NUM_PHASES][SRC_FF3_FIR_TAPS_PER_PHASE];
#endif // _SRC_FF3_COEFS_H_

70
lib_src/lib_src/src/fixed_factor_vpu_voice/src_low_level.h Normal file
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// Copyright 2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _SRC_LOW_LEVEL_H_
#define _SRC_LOW_LEVEL_H_
/**
* @brief Perfoms VPU-optimised convolution for s32 type integers
*
* @param samples Samples array
* @param coef FIR coefficients array
* @note Both samples and coef has to have 24 values int32_t in them
* @note Both samples and coef have to be 8 bit aligned
*/
int32_t conv_s32_24t(const int32_t * samples, const int32_t * coef);
/**
* @brief Perforns VPU-optimised FIR filtering for s32 type integers
*
* @param state State that keep previous samples
* @param coef FIR coefficients array
* @param new_samp New sample to put in the state
* @note Both state and coef has to have 24 values int32_t in them
* @note Both state and coef have to be 8 bit aligned
*/
int32_t fir_s32_24t(int32_t * state, const int32_t * coef, int32_t new_samp);
/**
* @brief Perfoms VPU-optimised convolution for s32 type integers
*
* @param samples Samples array
* @param coef FIR coefficients array
* @note Both samples and coef has to have 32 values int32_t in them
* @note Both samples and coef have to be 8 bit aligned
*/
int32_t conv_s32_32t(const int32_t * samples, const int32_t * coef);
/**
* @brief Perforns VPU-optimised FIR filtering for s32 type integers
*
* @param state State that keep previous samples
* @param coef FIR coefficients array
* @param new_samp New sample to put in the state
* @note Both state and coef has to have 32 values int32_t in them
* @note Both state and coef have to be 8 bit aligned
*/
int32_t fir_s32_32t(int32_t * state, const int32_t * coef, int32_t new_samp);
/**
* @brief Perforns VPU-optimised ring buffer shift for s32 type integers
*
* @param state State that keep previous samples
* @param new_samp New sample to put in the state
* @note Both state and coef has to have 48 values int32_t in them
* @note Both state and coef have to be 8 bit aligned
*/
void push_s32_48t(int32_t * state, int32_t new_samp);
/**
* @brief Perforns VPU-optimised FIR filtering for s32 type integers
*
* @param state State that keep previous samples
* @param coef FIR coefficients array
* @param new_samp New sample to put in the state
* @note Both state and coef has to have 48 values int32_t in them
* @note Both state and coef have to be 8 bit aligned
*/
int32_t fir_s32_48t(int32_t * state, const int32_t * coef, int32_t new_samp);
#endif // _SRC_LOW_LEVEL_H_

154
lib_src/lib_src/src/fixed_factor_vpu_voice/src_poly.h Normal file
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@@ -0,0 +1,154 @@
// Copyright 2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _SRC_POLY_VPU_H_
#define _SRC_POLY_VPU_H_
#include "stdint.h"
#include "src_low_level.h"
// If you want to undestand any of this better,
// read Richard G. Lyons "Understanding digital signal processing"
// capters 10.1 - 10.7, 10.10 - 10.11
/**
* @brief Performs VPU-optimised 72 taps polyphase fixed-factor-of-3 downsampling
*
* @param samp_in Values to be downsampled
* @param samp_out Downsampled output
* @param coefs_ff3 Three-phase FIR coefficients array with [3][24] dimensions
* @param state_ds Three-phase FIR state array with [3][24] dimensions
*/
static inline void src_ff3_72t_ds(int32_t samp_in[3], int32_t samp_out[1], const int32_t coefs_ff3[3][24], int32_t state_ds[3][24])
{
int64_t acc = 0;
acc += fir_s32_24t(state_ds[0], coefs_ff3[0], samp_in[0]);
acc += fir_s32_24t(state_ds[1], coefs_ff3[1], samp_in[1]);
acc += fir_s32_24t(state_ds[2], coefs_ff3[2], samp_in[2]);
samp_out[0] = (int32_t)acc;
}
/**
* @brief Performs VPU-optimised 72 taps polyphase fixed-factor-of-3 upsampling
*
* @param samp_in Value to be upsampled
* @param samp_out Upsampled output
* @param coefs_ff3 Three-phase FIR coefficients array with [3][24] dimensions
* @param state_us FIR state array with 24 elements in it
* @note samp_in and samp_out have to be different memory locations
*/
static inline void src_ff3_72t_us(int32_t samp_in[1], int32_t samp_out[3], const int32_t coefs_ff3[3][24], int32_t state_us[24])
{
samp_out[0] = fir_s32_24t(state_us, coefs_ff3[2], samp_in[0]) * 3;
samp_out[1] = conv_s32_24t(state_us, coefs_ff3[1]) * 3;
samp_out[2] = conv_s32_24t(state_us, coefs_ff3[0]) * 3;
}
/**
* \addtogroup src_ff3_96t_ds src_ff3_96t_ds
*
* The public API for using SRC.
* @{
*/
/**
* @brief Performs VPU-optimised 96 taps polyphase fixed-factor-of-3 downsampling
*
* @param samp_in Values to be downsampled
* @param samp_out Downsampled output
* @param coefs_ff3 Three-phase FIR coefficients array with [3][32] dimensions
* @param state_ds Three-phase FIR state array with [3][32] dimensions
*/
static inline void src_ff3_96t_ds(int32_t samp_in[3], int32_t samp_out[1], const int32_t coefs_ff3[3][32], int32_t state_ds[3][32])
{
int64_t acc = 0;
acc += fir_s32_32t(state_ds[0], coefs_ff3[0], samp_in[0]);
acc += fir_s32_32t(state_ds[1], coefs_ff3[1], samp_in[1]);
acc += fir_s32_32t(state_ds[2], coefs_ff3[2], samp_in[2]);
samp_out[0] = (int32_t)acc;
}
/**@}*/ // END: addtogroup src_ff3_96t_ds
/**
* \addtogroup src_ff3_96t_us src_ff3_96t_us
*
* The public API for using SRC.
* @{
*/
/**
* @brief Performs VPU-optimised 96 taps polyphase fixed-factor-of-3 upsampling
*
* @param samp_in Value to be upsampled
* @param samp_out Upsampled output
* @param coefs_ff3 Three-phase FIR coefficients array with [3][32] dimensions
* @param state_us FIR state array with 32 elements in it
* @note samp_in and samp_out have to be different memory locations
*/
static inline void src_ff3_96t_us(int32_t samp_in[1], int32_t samp_out[3], const int32_t coefs_ff3[3][32], int32_t state_us[32])
{
samp_out[0] = fir_s32_32t(state_us, coefs_ff3[2], samp_in[0]) * 3;
samp_out[1] = conv_s32_32t(state_us, coefs_ff3[1]) * 3;
samp_out[2] = conv_s32_32t(state_us, coefs_ff3[0]) * 3;
}
/**@}*/ // END: addtogroup src_ff3_96t_us
/**
* \addtogroup src_rat_2_3_96t_ds src_rat_2_3_96t_ds
*
* The public API for using SRC.
* @{
*/
/**
* @brief Performs VPU-optimised 96 taps polyphase rational factor 2/3 downsampling
*
* @param samp_in Values to be downsampled
* @param samp_out Downsampled output
* @param coefs_ds Two-phase FIR coefficients array with [2][48] dimensions
* @param state_ds FIR state array with 48 elements in it
*/
static inline void src_rat_2_3_96t_ds(int32_t samp_in[3], int32_t samp_out[2], const int32_t coefs_ds[2][48], int32_t state_ds[48])
{
push_s32_48t(state_ds, samp_in[0]);
samp_out[0] = fir_s32_48t(state_ds, coefs_ds[0], samp_in[1]) * 2;
samp_out[1] = fir_s32_48t(state_ds, coefs_ds[1], samp_in[2]) * 2;
}
/**@}*/ // END: addtogroup src_rat_2_3_96t_ds
/**
* \addtogroup src_rat_3_2_96t_us src_rat_3_2_96t_us
*
* The public API for using SRC.
* @{
*/
/**
* @brief Performs VPU-optimised 96 taps polyphase rational factor 3/2 upsampling
*
* @param samp_in Values to be upsampled
* @param samp_out Upsampled output
* @param coefs_us Three-phase FIR coefficients array with [3][32] dimensions
* @param state_us FIR state array with 32 elements in it
* @note samp_in and samp_out have to be different memory locations
*/
static inline void src_rat_3_2_96t_us(int32_t samp_in[2], int32_t samp_out[3], const int32_t coefs_us[3][32], int32_t state_us[32])
{
samp_out[0] = fir_s32_32t(state_us, coefs_us[0], samp_in[0]) * 3;
samp_out[1] = conv_s32_32t(state_us, coefs_us[2]) * 3;
samp_out[2] = fir_s32_32t(state_us, coefs_us[1], samp_in[1]) * 3;
}
/**@}*/ // END: addtogroup src_rat_3_2_96t_us
#endif // _SRC_POLY_VPU_H_

64
lib_src/lib_src/src/fixed_factor_vpu_voice/src_rat_fir_coefs.c Normal file
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@@ -0,0 +1,64 @@
// Copyright 2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
/*********************************/
/* AUTOGENERATED. DO NOT MODIFY! */
/*********************************/
// Use src_rat_fir_gen.py script to regenare this file
// python src_rat_fir_gen.py -gc True -nt 96
#include "src_rat_fir_coefs.h"
#include <stdint.h>
/** q30 coefficients to use for the 48 -> 32 kHz polyphase rational factor downsampling */
const int32_t ALIGNMENT(8) src_rat_fir_ds_coefs[SRC_RAT_FIR_NUM_PHASES_DS][SRC_RAT_FIR_TAPS_PER_PHASE_DS] = {
{
-37518, -12954, 215278, -239478, -263107, 939176,
-724308, -879964, 2499126, -1681211, -2092592, 5401196,
-3401730, -4251005, 10510310, -6447506, -8092907, 19936433,
-12408241, -16117127, 42378484, -29745967, -48209846, 227198230,
341824286, 67661646, -73999660, 25030944, 18189153, -28205672,
11237632, 8863615, -14437276, 5881230, 4701938, -7597786,
3022648, 2420957, -3741363, 1394185, 1128882, -1587718,
513087, 436331, -497504, 103937, 112484, -52024,
},
{
-52024, 112484, 103937, -497504, 436331, 513087,
-1587718, 1128882, 1394185, -3741363, 2420957, 3022648,
-7597786, 4701938, 5881230, -14437276, 8863615, 11237632,
-28205672, 18189153, 25030944, -73999660, 67661646, 341824286,
227198230, -48209846, -29745967, 42378484, -16117127, -12408241,
19936433, -8092907, -6447506, 10510310, -4251005, -3401730,
5401196, -2092592, -1681211, 2499126, -879964, -724308,
939176, -263107, -239478, 215278, -12954, -37518,
},
};
/** q30 coefficients to use for the 32 -> 48 kHz polyphase rational factor upsampling */
const int32_t ALIGNMENT(8) src_rat_fir_us_coefs[SRC_RAT_FIR_NUM_PHASES_US][SRC_RAT_FIR_TAPS_PER_PHASE_US] = {
{
-37518, 112484, -239478, 436331, -724308, 1128882,
-1681211, 2420957, -3401730, 4701938, -6447506, 8863615,
-12408241, 18189153, -29745967, 67661646, 341824286, -48209846,
25030944, -16117127, 11237632, -8092907, 5881230, -4251005,
3022648, -2092592, 1394185, -879964, 513087, -263107,
103937, -12954,},
{
-52024, 215278, -497504, 939176, -1587718, 2499126,
-3741363, 5401196, -7597786, 10510310, -14437276, 19936433,
-28205672, 42378484, -73999660, 227198230, 227198230, -73999660,
42378484, -28205672, 19936433, -14437276, 10510310, -7597786,
5401196, -3741363, 2499126, -1587718, 939176, -497504,
215278, -52024,},
{
-12954, 103937, -263107, 513087, -879964, 1394185,
-2092592, 3022648, -4251005, 5881230, -8092907, 11237632,
-16117127, 25030944, -48209846, 341824286, 67661646, -29745967,
18189153, -12408241, 8863615, -6447506, 4701938, -3401730,
2420957, -1681211, 1128882, -724308, 436331, -239478,
112484, -37518,},
};

37
lib_src/lib_src/src/fixed_factor_vpu_voice/src_rat_fir_coefs.h Normal file
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@@ -0,0 +1,37 @@
// Copyright 2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
/*********************************/
/* AUTOGENERATED. DO NOT MODIFY! */
/*********************************/
// Use src_rat_fir_gen.py script to regenare this file
// python src_rat_fir_gen.py -gc True -nt 96
#ifndef _SRC_RAT_COEFS_H_
#define _SRC_RAT_COEFS_H_
#include <stdint.h>
#ifndef ALIGNMENT
# ifdef __xcore__
# define ALIGNMENT(N) __attribute__((aligned (N)))
# else
# define ALIGNMENT(N)
# endif
#endif
#define SRC_RAT_FIR_NUM_TAPS (96)
#define SRC_RAT_FIR_NUM_PHASES_DS (2)
#define SRC_RAT_FIR_TAPS_PER_PHASE_DS (48)
#define SRC_RAT_FIR_NUM_PHASES_US (3)
#define SRC_RAT_FIR_TAPS_PER_PHASE_US (32)
/** q30 coefficients to use for the 48 -> 32 kHz polyphase rational factor downsampling */
extern const int32_t src_rat_fir_ds_coefs[SRC_RAT_FIR_NUM_PHASES_DS][SRC_RAT_FIR_TAPS_PER_PHASE_DS];
/** q30 coefficients to use for the 32 -> 48 kHz polyphase rational factor upsampling */
extern const int32_t src_rat_fir_us_coefs[SRC_RAT_FIR_NUM_PHASES_US][SRC_RAT_FIR_TAPS_PER_PHASE_US];
#endif // _SRC_RAT_COEFS_H_

1922
lib_src/lib_src/src/multirate_hifi/FilterData/ADFir.dat Normal file
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lib_src/lib_src/src/multirate_hifi/FilterData/ADFir.sfp Normal file
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146
lib_src/lib_src/src/multirate_hifi/FilterData/BL.dat Normal file
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@@ -0,0 +1,146 @@
4084,
22854,
52180,
39395,
-78621,
-243300,
-252701,
-27685,
159757,
11667,
-247746,
-115683,
280119,
215393,
-331173,
-372062,
355638,
570150,
-353372,
-821087,
305094,
1124112,
-195835,
-1480384,
5655,
1886268,
286062,
-2335369,
-701573,
2817885,
1264995,
-3319400,
-2001423,
3820542,
2936209,
-4297256,
-4095319,
4720234,
5505636,
-5053395,
-7193471,
5255380,
9187349,
-5276420,
-11516938,
5058910,
14216600,
-4533971,
-17327743,
3618612,
20905173,
-2208339,
-25024691,
168320,
29801046,
2688694,
-35412940,
-6636421,
42156519,
12107736,
-50551264,
-19850848,
61576623,
31301922,
-77293704,
-49656486,
102809719,
83785579,
-154988931,
-170966127,
340824123,
945102387,
945102387,
340824123,
-170966127,
-154988931,
83785579,
102809719,
-49656486,
-77293704,
31301922,
61576623,
-19850848,
-50551264,
12107736,
42156519,
-6636421,
-35412940,
2688694,
29801046,
168320,
-25024691,
-2208339,
20905173,
3618612,
-17327743,
-4533971,
14216600,
5058910,
-11516938,
-5276420,
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lib_src/lib_src/src/multirate_hifi/FilterData/scale_dat.py Normal file
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@@ -0,0 +1,17 @@
from argparse import ArgumentParser
from pathlib import Path
parse = ArgumentParser()
parse.add_argument("SCALE_FACTOR", type=float, help="number to scale all the filters by")
args = parse.parse_args()
for filepath in Path(__file__).parent.glob("*.dat"):
data_txt = filepath.read_text()
data = list(float(d.strip()) for d in data_txt.strip().split(",") if len(d))
data = [int(round(args.SCALE_FACTOR * i)) for i in data]
data = " " + ",\n ".join(str(d) for d in data) + "\n\n\n"
filepath.write_text(data)

732
lib_src/lib_src/src/multirate_hifi/asrc/src_mrhf_asrc.c Normal file
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@@ -0,0 +1,732 @@
// Copyright 2016-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
// ===========================================================================
// ===========================================================================
//
// File: asrc.c
//
//
// Top level implementation file for the ASRC
//
// ===========================================================================
// ===========================================================================
// ===========================================================================
//
// Includes
//
// ===========================================================================
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
#include "use_vpu.h"
// Integer arithmetic include
#include "src_mrhf_int_arithmetic.h"
// ASRC include
#include "src.h"
// ===========================================================================
//
// Defines
//
// ===========================================================================
// State init value
#define ASRC_STATE_INIT 0
// Nominal Fs Ratio values
#define ASRC_FS_44_F (44100.0)
#define ASRC_FS_48_F (48000.0)
#define ASRC_FS_88_F (88200.0)
#define ASRC_FS_96_F (96000.0)
#define ASRC_FS_176_F (176400.0)
#define ASRC_FS_192_F (192000.0)
#define ASRC_FS_RATIO_44_44 (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_44_44_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_44_48 (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_44_48_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_44_88 (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_44_88_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_44_96 (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_44_96_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_44_176 (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_44_176_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_44_192 (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_44_192_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_44_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_48_44 (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_48_44_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_48_48 (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_48_48_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_48_88 (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_48_88_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_48_96 (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_48_96_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_48_176 (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_48_176_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_48_192 (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_48_192_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_48_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_88_44 (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_88_44_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_88_48 (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_88_48_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_88_88 (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_88_88_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_88_96 (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_88_96_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_88_176 (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_88_176_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_88_192 (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_88_192_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_88_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_96_44 (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_96_44_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_96_48 (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_96_48_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_96_88 (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_96_88_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_96_96 (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_96_96_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_96_176 (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_96_176_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_96_192 (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_96_192_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_96_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_176_44 (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_176_44_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_176_48 (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_176_48_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_176_88 (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_176_88_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_176_96 (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_176_96_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_176_176 (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_176_176_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_176_192 (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_176_192_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_176_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_192_44 (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_192_44_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_44_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_192_48 (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_192_48_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_48_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_192_88 (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_192_88_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_88_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_192_96 (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_192_96_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_96_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_192_176 (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_192_176_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_176_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_192_192 (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))) >> 32)
#define ASRC_FS_RATIO_192_192_LO (uint32_t)((unsigned long long)(((double)ASRC_FS_192_F / ASRC_FS_192_F) * ((unsigned long long)1 << (ASRC_FS_RATIO_UNIT_BIT + 32))))
#define ASRC_FS_RATIO_MIN_FACTOR (0.99)
#define ASRC_FS_RATIO_MAX_FACTOR (1.01)
#define ASRC_ADFIR_INITIAL_PHASE 32
// Time ratio shift values
#define ASRC_FS_RATIO_PHASE_N_BITS 7
#define ASRC_FS_RATIO_BASE_SHIFT (ASRC_FS_RATIO_UNIT_BIT - ASRC_FS_RATIO_PHASE_N_BITS)
#define ASRC_FS_RATIO_SHIFT_M1 (ASRC_FS_RATIO_BASE_SHIFT + 1)
#define ASRC_FS_RATIO_SHIFT_0 (ASRC_FS_RATIO_BASE_SHIFT)
#define ASRC_FS_RATIO_SHIFT_P1 (ASRC_FS_RATIO_BASE_SHIFT - 1)
// Random number generator / dithering
#define ASRC_R_CONS 32767
#define ASRC_R_BASE 1664525
#define ASRC_RPDF_BITS_SHIFT 16 // Shift to select bits in pseudo-random number
#define ASRC_RPDF_MASK 0x0000007F // For dithering at 24bits (in 2.30)
#define ASRC_DATA24_MASK 0xFFFFFF00 // Mask for 24bits data (once rescaled to 1.31)
#define ASRC_DITHER_BIAS 0xFFFFFFC0 // TPDF dither bias for compensating masking at 24bits but expressed in 2.30
// ===========================================================================
//
// Variables
//
// ===========================================================================
ASRCFiltersIDs_t sASRCFiltersIDs[ASRC_N_FS][ASRC_N_FS] = // Filter configuration table [Fsin][Fsout]
{
{ // Fsin = 44.1kHz
// F1 F2
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 44.1kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 48kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 88.2kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 96kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 176.4kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}} // Fsout = 192kHz
},
{ // Fsin = 48kHz
// F1 F2
{{FILTER_DEFS_ASRC_FIR_UP4844_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 44.1kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 48kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 88.2kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 96kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 176.4kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}} // Fsout = 192kHz
},
{ // Fsin = 88.2kHz
// F1 F2
{{FILTER_DEFS_ASRC_FIR_BL_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 44.1kHz
{{FILTER_DEFS_ASRC_FIR_BL8848_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 48kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 88.2kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 96kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 176.4kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}} // Fsout = 192kHz
},
{ // Fsin = 96kHz
// F1 F2
{{FILTER_DEFS_ASRC_FIR_BL9644_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 44.1kHz
{{FILTER_DEFS_ASRC_FIR_BL_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 48kHz
{{FILTER_DEFS_ASRC_FIR_UP4844_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 88.2kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 96kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 176.4kHz
{{FILTER_DEFS_ASRC_FIR_UP_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}} // Fsout = 192kHz
},
{ // Fsin = 176.4kHz
// F1 F2
{{FILTER_DEFS_ASRC_FIR_DS_ID, FILTER_DEFS_ASRC_FIR_BL_ID}}, // Fsout = 44.1kHz
{{FILTER_DEFS_ASRC_FIR_DS_ID, FILTER_DEFS_ASRC_FIR_BL8848_ID}}, // Fsout = 48kHz
{{FITLER_DEFS_ASRC_FIR_BLF_ID, FILTER_DEFS_ASRC_FIR_NONE_ID,}}, // Fsout = 88.2kHz
{{FILTER_DEFS_ASRC_FIR_BL17696_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 96kHz
{{FILTER_DEFS_ASRC_FIR_UPF_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 176.4kHz
{{FILTER_DEFS_ASRC_FIR_UPF_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}} // Fsout = 192kHz
},
{ // Fsin = 192kHz
// F1 F2
{{FILTER_DEFS_ASRC_FIR_DS_ID, FILTER_DEFS_ASRC_FIR_BL9644_ID}}, // Fsout = 44.1kHz
{{FILTER_DEFS_ASRC_FIR_DS_ID, FILTER_DEFS_ASRC_FIR_BL_ID}}, // Fsout = 48kHz
{{FITLER_DEFS_ASRC_FIR_BL19288_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 88.2kHz
{{FITLER_DEFS_ASRC_FIR_BLF_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 96kHz
{{FILTER_DEFS_ASRC_FIR_UP192176_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}}, // Fsout = 176.4kHz
{{FILTER_DEFS_ASRC_FIR_UPF_ID, FILTER_DEFS_ASRC_FIR_NONE_ID}} // Fsout = 192kHz
}
};
ASRCFsRatioConfigs_t sFsRatioConfigs[ASRC_N_FS][ASRC_N_FS] = // Fs ratio configuration table [Fsin][Fsout]
{
{ // Fsin = 44.1kHz
// Nominal Fs Ratio // Minimal Fs Ratio // Maximal Fs Ratio Shift for time step
{ASRC_FS_RATIO_44_44, ASRC_FS_RATIO_44_44_LO, (unsigned int)(ASRC_FS_RATIO_44_44 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_44_44 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 44.1kHz
{ASRC_FS_RATIO_44_48, ASRC_FS_RATIO_44_48_LO, (unsigned int)(ASRC_FS_RATIO_44_48 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_44_48 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 48kHz
{ASRC_FS_RATIO_44_88, ASRC_FS_RATIO_44_88_LO, (unsigned int)(ASRC_FS_RATIO_44_88 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_44_88 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 88.2kHz
{ASRC_FS_RATIO_44_96, ASRC_FS_RATIO_44_96_LO, (unsigned int)(ASRC_FS_RATIO_44_96 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_44_96 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 96kHz
{ASRC_FS_RATIO_44_176, ASRC_FS_RATIO_44_176_LO, (unsigned int)(ASRC_FS_RATIO_44_176 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_44_176 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 176.4kHz
{ASRC_FS_RATIO_44_192, ASRC_FS_RATIO_44_192_LO, (unsigned int)(ASRC_FS_RATIO_44_192 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_44_192 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1} // Fsout = 192kHz
},
{ // Fsin = 48kHz
// Nominal Fs Ratio // Minimal Fs Ratio // Maximal Fs Ratio Shift for time step
{ASRC_FS_RATIO_48_44, ASRC_FS_RATIO_48_44_LO, (unsigned int)(ASRC_FS_RATIO_48_44 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_48_44 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 44.1kHz
{ASRC_FS_RATIO_48_48, ASRC_FS_RATIO_48_48_LO, (unsigned int)(ASRC_FS_RATIO_48_48 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_48_48 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 48kHz
{ASRC_FS_RATIO_48_88, ASRC_FS_RATIO_48_88_LO, (unsigned int)(ASRC_FS_RATIO_48_88 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_48_88 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 88.2kHz
{ASRC_FS_RATIO_48_96, ASRC_FS_RATIO_48_96_LO, (unsigned int)(ASRC_FS_RATIO_48_96 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_48_96 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 96kHz
{ASRC_FS_RATIO_48_176, ASRC_FS_RATIO_48_176_LO, (unsigned int)(ASRC_FS_RATIO_48_176 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_48_176 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 176.4kHz
{ASRC_FS_RATIO_48_192, ASRC_FS_RATIO_48_192_LO, (unsigned int)(ASRC_FS_RATIO_48_192 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_48_192 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1} // Fsout = 192kHz
},
{ // Fsin = 88.2kHz
// Nominal Fs Ratio // Minimal Fs Ratio // Maximal Fs Ratio Shift for time step
{ASRC_FS_RATIO_88_44, ASRC_FS_RATIO_88_44_LO, (unsigned int)(ASRC_FS_RATIO_88_44 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_88_44 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_0}, // Fsout = 44.1kHz
{ASRC_FS_RATIO_88_48, ASRC_FS_RATIO_88_48_LO, (unsigned int)(ASRC_FS_RATIO_88_48 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_88_48 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_0}, // Fsout = 48kHz
{ASRC_FS_RATIO_88_88, ASRC_FS_RATIO_88_88_LO, (unsigned int)(ASRC_FS_RATIO_88_88 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_88_88 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 88.2kHz
{ASRC_FS_RATIO_88_96, ASRC_FS_RATIO_88_96_LO, (unsigned int)(ASRC_FS_RATIO_88_96 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_88_96 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 96kHz
{ASRC_FS_RATIO_88_176, ASRC_FS_RATIO_88_176_LO, (unsigned int)(ASRC_FS_RATIO_88_176 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_88_176 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 176.4kHz
{ASRC_FS_RATIO_88_192, ASRC_FS_RATIO_88_192_LO, (unsigned int)(ASRC_FS_RATIO_88_192 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_88_192 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1} // Fsout = 192kHz
},
{ // Fsin = 96kHz
// Nominal Fs Ratio // Minimal Fs Ratio // Maximal Fs Ratio Shift for time step
{ASRC_FS_RATIO_96_44, ASRC_FS_RATIO_96_44_LO, (unsigned int)(ASRC_FS_RATIO_96_44 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_96_44 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_0}, // Fsout = 44.1kHz
{ASRC_FS_RATIO_96_48, ASRC_FS_RATIO_96_48_LO, (unsigned int)(ASRC_FS_RATIO_96_48 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_96_48 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_0}, // Fsout = 48kHz
{ASRC_FS_RATIO_96_88, ASRC_FS_RATIO_96_88_LO, (unsigned int)(ASRC_FS_RATIO_96_88 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_96_88 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 88.2kHz
{ASRC_FS_RATIO_96_96, ASRC_FS_RATIO_96_96_LO, (unsigned int)(ASRC_FS_RATIO_96_96 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_96_96 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 96kHz
{ASRC_FS_RATIO_96_176, ASRC_FS_RATIO_96_176_LO, (unsigned int)(ASRC_FS_RATIO_96_176 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_96_176 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 176.4kHz
{ASRC_FS_RATIO_96_192, ASRC_FS_RATIO_96_192_LO, (unsigned int)(ASRC_FS_RATIO_96_192 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_96_192 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1} // Fsout = 192kHz
},
{ // Fsin = 176.4kHz
// Nominal Fs Ratio // Minimal Fs Ratio // Maximal Fs Ratio Shift for time step
{ASRC_FS_RATIO_176_44, ASRC_FS_RATIO_176_44_LO, (unsigned int)(ASRC_FS_RATIO_176_44 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_176_44 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_M1}, // Fsout = 44.1kHz
{ASRC_FS_RATIO_176_48, ASRC_FS_RATIO_176_48_LO, (unsigned int)(ASRC_FS_RATIO_176_48 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_176_48 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_M1}, // Fsout = 48kHz
{ASRC_FS_RATIO_176_88, ASRC_FS_RATIO_176_88_LO, (unsigned int)(ASRC_FS_RATIO_176_88 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_176_88 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_0}, // Fsout = 88.2kHz
{ASRC_FS_RATIO_176_96, ASRC_FS_RATIO_176_96_LO, (unsigned int)(ASRC_FS_RATIO_176_96 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_176_96 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_0}, // Fsout = 96kHz
{ASRC_FS_RATIO_176_176, ASRC_FS_RATIO_176_176_LO, (unsigned int)(ASRC_FS_RATIO_176_176 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_176_176 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 176.4kHz
{ASRC_FS_RATIO_176_192, ASRC_FS_RATIO_176_192_LO, (unsigned int)(ASRC_FS_RATIO_176_192 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_176_192 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1} // Fsout = 192kHz
},
{ // Fsin = 192kHz
// Nominal Fs Ratio // Minimal Fs Ratio // Maximal Fs Ratio Shift for time step
{ASRC_FS_RATIO_192_44, ASRC_FS_RATIO_192_44_LO, (unsigned int)(ASRC_FS_RATIO_192_44 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_192_44 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_M1}, // Fsout = 44.1kHz
{ASRC_FS_RATIO_192_48, ASRC_FS_RATIO_192_48_LO, (unsigned int)(ASRC_FS_RATIO_192_48 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_192_48 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_M1}, // Fsout = 48kHz
{ASRC_FS_RATIO_192_88, ASRC_FS_RATIO_192_88_LO, (unsigned int)(ASRC_FS_RATIO_192_88 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_192_88 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_0}, // Fsout = 88.2kHz
{ASRC_FS_RATIO_192_96, ASRC_FS_RATIO_192_96_LO, (unsigned int)(ASRC_FS_RATIO_192_96 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_192_96 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_0}, // Fsout = 96kHz
{ASRC_FS_RATIO_192_176, ASRC_FS_RATIO_192_176_LO, (unsigned int)(ASRC_FS_RATIO_192_176 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_192_176 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1}, // Fsout = 176.4kHz
{ASRC_FS_RATIO_192_192, ASRC_FS_RATIO_192_192_LO, (unsigned int)(ASRC_FS_RATIO_192_192 * ASRC_FS_RATIO_MIN_FACTOR), (unsigned int)(ASRC_FS_RATIO_192_192 * ASRC_FS_RATIO_MAX_FACTOR), ASRC_FS_RATIO_SHIFT_P1} // Fsout = 192kHz
}
};
// ===========================================================================
//
// Local Functions prototypes
//
// ===========================================================================
// ===========================================================================
//
// Functions implementations
//
// ===========================================================================
#if SRC_USE_VPU
#define xs3_index_shuffle(a,b) [(b)^7][a]
#else
#define xs3_index_shuffle(a,b) [a][b]
#endif
// ==================================================================== //
// Function: ASRC_prepare_coefs //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Prepares the ASRC coefficients from the prototype //
// Needs to be called only once //
// ==================================================================== //
ASRCReturnCodes_t ASRC_prepare_coefs(void)
{
unsigned int ui, uj;
int* piPrototypeCoefs = iADFirPrototypeCoefs + FILTER_DEFS_ADFIR_PROTOTYPE_N_TAPS - FILTER_DEFS_ADFIR_N_PHASES;
// First fill in the phases which start normally
for(ui = 0; ui < FILTER_DEFS_ADFIR_N_PHASES; ui++)
{
// Copy phase information
for(uj = 0; uj < FILTER_DEFS_ADFIR_PHASE_N_TAPS - 1; uj++)
iADFirCoefs xs3_index_shuffle(ui, uj) = *(piPrototypeCoefs + ui - uj * FILTER_DEFS_ADFIR_N_PHASES);
// Zero fill last coefficient
iADFirCoefs xs3_index_shuffle(ui, FILTER_DEFS_ADFIR_PHASE_N_TAPS - 1) = 0;
}
// Then fill in the two phases which start delayed
for(ui = 0; ui < 2; ui++)
{
// Zero fill first coefficient
iADFirCoefs xs3_index_shuffle(FILTER_DEFS_ADFIR_N_PHASES + ui, 0) = 0;
// Copy phase informaiton
for(uj = 0; uj < FILTER_DEFS_ADFIR_PHASE_N_TAPS - 1; uj++)
iADFirCoefs xs3_index_shuffle(FILTER_DEFS_ADFIR_N_PHASES + ui,uj + 1) = *(piPrototypeCoefs + ui - uj * FILTER_DEFS_ADFIR_N_PHASES);
}
return ASRC_NO_ERROR;
}
// ==================================================================== //
// Function: ASRC_init //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Inits the ASRC passed as argument //
// ==================================================================== //
ASRCReturnCodes_t ASRC_init(asrc_ctrl_t* pasrc_ctrl)
{
ASRCFiltersIDs_t* psFiltersID;
FIRDescriptor_t* psFIRDescriptor;
ADFIRDescriptor_t* psADFIRDescriptor;
// Check if state is allocated
if(pasrc_ctrl->psState == 0)
return ASRC_ERROR;
// Check if stack is allocated
if(pasrc_ctrl->piStack == 0)
return ASRC_ERROR;
// Check if valid Fsin and Fsout have been provided
if( (pasrc_ctrl->eInFs < ASRC_FS_MIN) || (pasrc_ctrl->eInFs > ASRC_FS_MAX))
return ASRC_ERROR;
if( (pasrc_ctrl->eOutFs < ASRC_FS_MIN) || (pasrc_ctrl->eOutFs > ASRC_FS_MAX))
return ASRC_ERROR;
// Set nominal fs ratio
pasrc_ctrl->uiFsRatio = sFsRatioConfigs[pasrc_ctrl->eInFs][pasrc_ctrl->eOutFs].uiNominalFsRatio;
pasrc_ctrl->uiFsRatio_lo = sFsRatioConfigs[pasrc_ctrl->eInFs][pasrc_ctrl->eOutFs].uiNominalFsRatio_lo;
// Check that number of input samples is allocated and is a multiple of 4
if(pasrc_ctrl->uiNInSamples == 0)
return ASRC_ERROR;
if((pasrc_ctrl->uiNInSamples & 0x3) != 0x0)
return ASRC_ERROR;
// Load filters ID and number of samples
psFiltersID = &sASRCFiltersIDs[pasrc_ctrl->eInFs][pasrc_ctrl->eOutFs];
// Configure filters F1 and F2 from filters ID and number of samples
// Filter F1
// ---------
psFIRDescriptor = &sASRCFirDescriptor[psFiltersID->uiFID[ASRC_F1_INDEX]];
// Set number of input samples and input samples step
pasrc_ctrl->sFIRF1Ctrl.uiNInSamples = pasrc_ctrl->uiNInSamples;
pasrc_ctrl->sFIRF1Ctrl.uiInStep = pasrc_ctrl->uiNchannels;
// Set delay line base pointer
if( psFiltersID->uiFID[ASRC_F1_INDEX] == FILTER_DEFS_ASRC_FIR_DS_ID )
pasrc_ctrl->sFIRF1Ctrl.piDelayB = pasrc_ctrl->psState->iDelayFIRShort;
else
pasrc_ctrl->sFIRF1Ctrl.piDelayB = pasrc_ctrl->psState->iDelayFIRLong;
// Set output buffer step
pasrc_ctrl->sFIRF1Ctrl.uiOutStep = 1;//ASRC_N_CHANNELS; //TODO confirm this
// Call init for FIR F1
if(FIR_init_from_desc(&pasrc_ctrl->sFIRF1Ctrl, psFIRDescriptor) != FIR_NO_ERROR)
return ASRC_ERROR;
// Update synchronous number of samples
if( psFiltersID->uiFID[ASRC_F1_INDEX] != FILTER_DEFS_ASRC_FIR_NONE_ID )
pasrc_ctrl->uiNSyncSamples = pasrc_ctrl->sFIRF1Ctrl.uiNOutSamples;
// Filter F2
// ---------
psFIRDescriptor = &sASRCFirDescriptor[psFiltersID->uiFID[ASRC_F2_INDEX]];
// Set number of input samples and input samples step
pasrc_ctrl->sFIRF2Ctrl.uiNInSamples = pasrc_ctrl->sFIRF1Ctrl.uiNOutSamples;
pasrc_ctrl->sFIRF2Ctrl.uiInStep = pasrc_ctrl->sFIRF1Ctrl.uiOutStep;
// Set delay line base pointer (second filter is always long with ASRC)
pasrc_ctrl->sFIRF2Ctrl.piDelayB = pasrc_ctrl->psState->iDelayFIRLong;
// Set output buffer step
pasrc_ctrl->sFIRF2Ctrl.uiOutStep = 1;//ASRC_N_CHANNELS; //TODO confirm this. Looks like 1 = channel per instance
// Call init for FIR F2
if(FIR_init_from_desc(&pasrc_ctrl->sFIRF2Ctrl, psFIRDescriptor) != FIR_NO_ERROR)
return ASRC_ERROR;
// Update synchronous number of samples
if( psFiltersID->uiFID[ASRC_F2_INDEX] != FILTER_DEFS_ASRC_FIR_NONE_ID )
pasrc_ctrl->uiNSyncSamples = pasrc_ctrl->sFIRF2Ctrl.uiNOutSamples;
// Setup fixed input/output buffers for F1 and F2
// ----------------------------------------------
// We set all fixed items (to stack base)
// F1 input is never from stack, so don't set it
pasrc_ctrl->sFIRF2Ctrl.piIn = pasrc_ctrl->piStack;
pasrc_ctrl->sFIRF1Ctrl.piOut = pasrc_ctrl->piStack;
pasrc_ctrl->sFIRF2Ctrl.piOut = pasrc_ctrl->piStack;
// Filter F3
// ---------
psADFIRDescriptor = &sADFirDescriptor;
// Set delay line base pointer
pasrc_ctrl->sADFIRF3Ctrl.piDelayB = pasrc_ctrl->psState->iDelayADFIR;
// Set AD coefficients pointer
pasrc_ctrl->sADFIRF3Ctrl.piADCoefs = pasrc_ctrl->piADCoefs;
// Call init for ADFIR F3
if(ADFIR_init_from_desc(&pasrc_ctrl->sADFIRF3Ctrl, psADFIRDescriptor) != FIR_NO_ERROR)
return ASRC_ERROR;
// Call sync function
if(ASRC_sync(pasrc_ctrl) != ASRC_NO_ERROR)
return ASRC_ERROR;
return ASRC_NO_ERROR;
}
// ==================================================================== //
// Function: ASRC_sync //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Syncs the ASRC passed as argument //
// ==================================================================== //
ASRCReturnCodes_t ASRC_sync(asrc_ctrl_t* pasrc_ctrl)
{
// Sync the FIR and ADFIR
if(FIR_sync(&pasrc_ctrl->sFIRF1Ctrl) != FIR_NO_ERROR)
return ASRC_ERROR;
if(FIR_sync(&pasrc_ctrl->sFIRF2Ctrl) != FIR_NO_ERROR)
return ASRC_ERROR;
if(ADFIR_sync(&pasrc_ctrl->sADFIRF3Ctrl) != FIR_NO_ERROR)
return ASRC_ERROR;
// Reset time
pasrc_ctrl->iTimeInt = FILTER_DEFS_ADFIR_N_PHASES + ASRC_ADFIR_INITIAL_PHASE;
pasrc_ctrl->uiTimeFract = 0;
// Reset random seeds to initial values
pasrc_ctrl->psState->uiRndSeed = pasrc_ctrl->uiRndSeedInit;
// Update time step based on Fs ratio
if(ASRC_update_fs_ratio(pasrc_ctrl) != ASRC_NO_ERROR)
return ASRC_ERROR;
return ASRC_NO_ERROR;
}
// ==================================================================== //
// Function: ASRC_proc_F1_F2 //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Processes F1 and F2 for a channel //
// ==================================================================== //
#if (XCC_VERSION_MAJOR < 1402) //Beyond 14.2.0 we have proper function pointer support for C
#pragma stackfunction 64 //Generous stack allocation (probably needs just a handful through F1_F2, ASM etc).
#endif
ASRCReturnCodes_t ASRC_proc_F1_F2(asrc_ctrl_t* pasrc_ctrl)
{
// Setup variable input / output buffers
pasrc_ctrl->sFIRF1Ctrl.piIn = pasrc_ctrl->piIn;
// F1 is always enabled, so call F1
__attribute__((fptrgroup("MRHF_G1")))
FIRReturnCodes_t ret = pasrc_ctrl->sFIRF1Ctrl.pvProc((int *)&pasrc_ctrl->sFIRF1Ctrl);
if(ret != FIR_NO_ERROR)
return ASRC_ERROR;
// Check if F2 is enabled
if(pasrc_ctrl->sFIRF2Ctrl.eEnable == FIR_ON)
{
// F2 is enabled, so call F2
__attribute__((fptrgroup("MRHF_G1")))
FIRReturnCodes_t ret = pasrc_ctrl->sFIRF2Ctrl.pvProc((int *)&pasrc_ctrl->sFIRF2Ctrl);
if(ret != FIR_NO_ERROR)
return ASRC_ERROR;
}
return ASRC_NO_ERROR;
}
// ==================================================================== //
// Function: ASRC_update_fs_ratio //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Updates the ASRC with the new Fs ratio //
// ==================================================================== //
ASRCReturnCodes_t ASRC_update_fs_ratio(asrc_ctrl_t* pasrc_ctrl)
{
unsigned int uiFsRatio = pasrc_ctrl->uiFsRatio;
unsigned int uiFsRatio_low = pasrc_ctrl->uiFsRatio_lo;
// Check for bounds of new Fs ratio
if( (uiFsRatio < sFsRatioConfigs[pasrc_ctrl->eInFs][pasrc_ctrl->eOutFs].uiMinFsRatio) ||
(uiFsRatio > sFsRatioConfigs[pasrc_ctrl->eInFs][pasrc_ctrl->eOutFs].uiMaxFsRatio) )
return ASRC_ERROR;
// Apply shift to time ratio to build integer and fractional parts of time step
pasrc_ctrl->iTimeStepInt = uiFsRatio >> (sFsRatioConfigs[pasrc_ctrl->eInFs][pasrc_ctrl->eOutFs].iFsRatioShift);
pasrc_ctrl->uiTimeStepFract = uiFsRatio << (32 - sFsRatioConfigs[pasrc_ctrl->eInFs][pasrc_ctrl->eOutFs].iFsRatioShift);
pasrc_ctrl->uiTimeStepFract |= (uint32_t)(uiFsRatio_low >> sFsRatioConfigs[pasrc_ctrl->eInFs][pasrc_ctrl->eOutFs].iFsRatioShift);
return ASRC_NO_ERROR;
}
// ==================================================================== //
// Function: ASRC_proc_F3_in_spl //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// int iInSample: new input sample //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Writes new input sample to F3 delay line //
// ==================================================================== //
ASRCReturnCodes_t ASRC_proc_F3_in_spl(asrc_ctrl_t* pasrc_ctrl, int iInSample)
{
pasrc_ctrl->sADFIRF3Ctrl.iIn = iInSample;
if(ADFIR_proc_in_spl(&pasrc_ctrl->sADFIRF3Ctrl) != FIR_NO_ERROR)
return ASRC_ERROR;
// Decrease next output time (this is an integer value, so no influence on fractional part)
pasrc_ctrl->iTimeInt -= FILTER_DEFS_ADFIR_N_PHASES;
return ASRC_NO_ERROR;
}
// ==================================================================== //
// Function: ASRC_proc_F3_time //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR if an output sample must be produced //
// ASRC_ERROR if no output sample needs to be produced //
// Description: Processes F3 time //
// ==================================================================== //
ASRCReturnCodes_t ASRC_proc_F3_time(asrc_ctrl_t* pasrc_ctrl)
{
unsigned int uiTemp;
int iAlpha;
int iH[3]; //iH0, iH1, iH2;
int iZero;
__int64_t i64Acc0;
int* piPhase0;
int* piADCoefs;
// Check if the next output time instant is in the current time slot
// -----------------------------------------------------------------
// if not return value showing that no output sample needs to be produced
// Update cycle count
if(pasrc_ctrl->iTimeInt >= FILTER_DEFS_ADFIR_N_PHASES)
return ASRC_ERROR;
// Update adaptive filter coefficients
// -----------------------------------
// Coefficients computation load approximation: 15 instructions
// Loop load approximation: 5.625 instructions per sample + 15 instructions overhead => 5.625 * 16 + 15 = 90 + 15 = 105 Instructions
// Total: 125 instructions
// Set register to zero
iZero = 0;
// Compute adative coefficients spline factors
// The fractional part of time gives alpha
iAlpha = pasrc_ctrl->uiTimeFract>>1; // Now alpha can be seen as a signed number
i64Acc0 = (long long)iAlpha * (long long)iAlpha;
#if SRC_USE_VPU
iH[2] = (int)(i64Acc0>>32);
iH[0] = 0x40000000; // Load H2 with 0.5;
iH[1] = iH[0] - iH[2]; // H1 = 0.5 - 0.5 * alpha * alpha;
iH[1] = iH[1] - iH[2]; // H1 = 0.5 - alpha * alpha
iH[1] = iH[1] + iAlpha; // H1 = 0.5 + alpha - alpha * alpha;
iH[0] = iH[0] - iAlpha; // H2 = 0.5 - alpha
iH[0] = iH[0] + iH[2]; // H2 = 0.5 - alpha + 0.5 * alpha * alpha
// The integer part of time gives the phase
piPhase0 = &iADFirCoefs[0][pasrc_ctrl->iTimeInt];
piADCoefs = pasrc_ctrl->piADCoefs; // Given limited number of registers, this should be DP
src_mrhf_spline_coeff_gen_inner_loop_asm_xs3(piPhase0, iH, piADCoefs, FILTER_DEFS_ADFIR_PHASE_N_TAPS);
#else
iH[0] = (int)(i64Acc0>>32);
iH[2] = 0x40000000; // Load H2 with 0.5;
iH[1] = iH[2] - iH[0]; // H1 = 0.5 - 0.5 * alpha * alpha;
iH[1] = iH[1] - iH[0]; // H1 = 0.5 - alpha * alpha
iH[1] = iH[1] + iAlpha; // H1 = 0.5 + alpha - alpha * alpha;
iH[2] = iH[2] - iAlpha; // H2 = 0.5 - alpha
iH[2] = iH[2] + iH[0]; // H2 = 0.5 - alpha + 0.5 * alpha * alpha
// The integer part of time gives the phase
piPhase0 = iADFirCoefs[pasrc_ctrl->iTimeInt];
piADCoefs = pasrc_ctrl->piADCoefs; // Given limited number of registers, this should be DP
src_mrhf_spline_coeff_gen_inner_loop_asm(piPhase0, iH, piADCoefs, FILTER_DEFS_ADFIR_PHASE_N_TAPS);
#endif
// Step time for next output sample
// --------------------------------
// Step to next output time (add integer and fractional parts)
pasrc_ctrl->iTimeInt += pasrc_ctrl->iTimeStepInt;
// For fractional part, this can be optimized using the add with carry instruction of XS2
uiTemp = pasrc_ctrl->uiTimeFract;
pasrc_ctrl->uiTimeFract += pasrc_ctrl->uiTimeStepFract;
if(pasrc_ctrl->uiTimeFract < uiTemp)
pasrc_ctrl->iTimeInt++;
//printf("TimeInt = %x TimeFract = %x", pasrc_ctrl->iTimeInt, pasrc_ctrl->uiTimeFract);
//int result=0; for (int i=0; i<16; i++)result += piADCoefs[i];printf("ASRC_proc_F3_time checksum=0x%x\n", result);
// Return value showing that an output sample must be produced
return ASRC_NO_ERROR;
}
// ==================================================================== //
// Function: ASRC_proc_F3_macc //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// int* piOutSample: Address of output sample //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Processes F3 for a channel //
// ==================================================================== //
ASRCReturnCodes_t ASRC_proc_F3_macc(asrc_ctrl_t* pasrc_ctrl, int* piOutSample)
{
pasrc_ctrl->sADFIRF3Ctrl.piOut = piOutSample;
// Call processing function
if(ADFIR_proc_macc(&pasrc_ctrl->sADFIRF3Ctrl) != FIR_NO_ERROR)
return ASRC_ERROR;
pasrc_ctrl->uiNASRCOutSamples++;
return ASRC_NO_ERROR;
}
// ==================================================================== //
// Function: ASRC_proc_dither //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Processes dither for a channel //
// ==================================================================== //
ASRCReturnCodes_t ASRC_proc_dither(asrc_ctrl_t* pasrc_ctrl)
{
int* piData;
unsigned int uiR;
int iDither;
__int64_t i64Acc;
unsigned int ui;
// Apply dither if required
if(pasrc_ctrl->uiDitherOnOff == ASRC_DITHER_ON)
{
// Get data buffer
piData = pasrc_ctrl->piOut;
// Get random seed
uiR = pasrc_ctrl->psState->uiRndSeed;
// Loop through samples
for(ui = 0; ui < pasrc_ctrl->uiNASRCOutSamples * pasrc_ctrl->uiNchannels; ui += pasrc_ctrl->uiNchannels)
{
// Compute dither sample (TPDF)
iDither = ASRC_DITHER_BIAS;
uiR = (unsigned int)(ASRC_R_BASE * uiR);
uiR = (unsigned int)(ASRC_R_CONS + uiR);
iDither += ((uiR>>ASRC_RPDF_BITS_SHIFT) & ASRC_RPDF_MASK);
uiR = (unsigned int)(ASRC_R_BASE * uiR);
uiR = (unsigned int)(ASRC_R_CONS + uiR);
iDither += ((uiR>>ASRC_RPDF_BITS_SHIFT) & ASRC_RPDF_MASK);
//unsigned iACCl = 0;
//int iACCh = iDither;
//pi_Data[ui] = dither_maths_asm(piData[ui],iACCh, iACCl);
// Use MACC instruction to saturate and dither + signal
i64Acc = ((__int64_t)iDither <<32); // On XMOS this is not necessary, just load dither in the top word of the ACC register
MACC(&i64Acc, piData[ui], 0x7FFFFFFF);
LSAT30(&i64Acc);
// Extract 32bits result
EXT30(&piData[ui], i64Acc);
// Mask to 24bits
piData[ui] &= ASRC_DATA24_MASK;
}
// Write random seed back
pasrc_ctrl->psState->uiRndSeed = uiR;
}
return ASRC_NO_ERROR;
}

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// Copyright 2016-2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
// ===========================================================================
// ===========================================================================
//
// Top level definition file for the ASRC
//
// Target: MS Windows
// Version: 1.0
//
// ===========================================================================
// ===========================================================================
#ifndef _SRC_MRHF_ASRC_H_
#define _SRC_MRHF_ASRC_H_
// ===========================================================================
//
// Includes
//
// ===========================================================================
#include "src_mrhf_fir.h"
#include "src_mrhf_filter_defs.h"
#include "src.h"
#include "src_mrhf_spline_coeff_gen_inner_loop_asm.h"
#include "src_mrhf_adfir_inner_loop_asm.h"
// ===========================================================================
//
// Defines
//
// ===========================================================================
// General defines
// ---------------
#define ASRC_FS_RATIO_UNIT_BIT 28
#define ASRC_STACK_LENGTH_MULT (ASRC_N_CHANNELS * 4) // Multiplier for stack length (stack length = this value x the number of input samples to process)
#define ASRC_ADFIR_COEFS_LENGTH FILTER_DEFS_ADFIR_PHASE_N_TAPS // Length of AD FIR coefficients buffer
#define ASRC_NOMINAL_FS_SCALE (1 << ASRC_FS_RATIO_UNIT_BIT)
// Parameter values
// ----------------
#define ASRC_DITHER_OFF 0
#define ASRC_DITHER_ON 1
#define ASRC_DITHER_ON_OFF_MIN ASRC_DITHER_OFF
#define ASRC_DITHER_ON_OFF_MAX ASRC_DITHER_ON
// ===========================================================================
//
// Defines
//
// ===========================================================================
// ===========================================================================
//
// TypeDefs
//
// ===========================================================================
// To avoid C type definitions when including this file from assembler
#ifndef INCLUDE_FROM_ASM
// ASRC Return Codes
// -----------------
typedef enum _ASRCReturnCodes
{
ASRC_NO_ERROR = 0,
ASRC_ERROR = 1
} ASRCReturnCodes_t;
// Sampling rate codes
// -------------------
typedef enum _ASRCFs
{
ASRC_FS_44 = 0, // Fs = 44.1kHz code
ASRC_FS_48 = 1, // Fs = 48kHz code
ASRC_FS_88 = 2, // Fs = 88.2kHz code
ASRC_FS_96 = 3, // Fs = 96kHz code
ASRC_FS_176 = 4, // Fs = 176.4kHz code
ASRC_FS_192 = 5, // Fs = 192kHz code
} ASRCFs_t;
#define ASRC_N_FS (ASRC_FS_192 + 1)
#define ASRC_FS_MIN ASRC_FS_44
#define ASRC_FS_MAX ASRC_FS_192
// ASRC Filters IDs structure
// --------------------------
#define ASRC_F1_INDEX 0
#define ASRC_F2_INDEX 1
#define ASRC_N_F (ASRC_F2_INDEX + 1)
typedef struct _ASRCFiltersIDs
{
unsigned int uiFID[ASRC_N_F];
} ASRCFiltersIDs_t;
// ASRC time ratio configurations
// ------------------------------
typedef struct _ASRCFsRatioConfigs
{
unsigned int uiNominalFsRatio;
unsigned int uiNominalFsRatio_lo;
unsigned int uiMinFsRatio;
unsigned int uiMaxFsRatio;
int iFsRatioShift;
} ASRCFsRatioConfigs_t;
// ASRC State structure
// --------------------
typedef struct _ASRCState
{
long long pad_to_64b_alignment; //Force compiler to 64b align
unsigned int uiRndSeed; // Dither random seeds current values
int iDelayFIRLong[2 * FILTER_DEFS_FIR_MAX_TAPS_LONG]; // Doubled length for circular buffer simulation
int iDelayFIRShort[2 * FILTER_DEFS_FIR_MAX_TAPS_SHORT]; // Doubled length for circular buffer simulation
int iDelayADFIR[2 * FILTER_DEFS_ADFIR_PHASE_N_TAPS]; // Doubled length for circular buffer simulation
} asrc_state_t;
// ASRC Control structure
// ----------------------
typedef struct _ASRCCtrl
{
#ifdef __XC__
long long pad_to_64b_alignment; //Force compiler to 64b align
unsigned int uiNchannels; // Number of channels in this instance
int* unsafe piIn; // Input buffer pointer (PCM, 32bits, 2 channels time domain interleaved data)
unsigned int uiNInSamples; // Number of input samples to process in one call to the processing function
unsigned int uiNSyncSamples; // Number of synchronous samples produced in one call to the processing function
ASRCFs_t eInFs; // Input sampling rate code
int* unsafe piOut; // Output buffer poin ter (PCM, 32bits, 2 channels time domain interleaved data)
unsigned int uiNASRCOutSamples; // Number of output samples produced during last call to the asynchronous processing function
ASRCFs_t eOutFs; // Output sampling rate code
FIRCtrl_t sFIRF1Ctrl; // F1 FIR controller
FIRCtrl_t sFIRF2Ctrl; // F2 FIR controller
ADFIRCtrl_t sADFIRF3Ctrl; // F3 ADFIR controller
unsigned int uiFsRatio; // Fs ratio: Fsin / Fsout
unsigned int uiFsRatio_lo;
int iTimeInt; // Integer part of time
unsigned int uiTimeFract; // Fractional part of time
int iTimeStepInt; // Integer part of time step
unsigned int uiTimeStepFract; // Fractional part of time step
unsigned int uiDitherOnOff; // Dither on/off flag
unsigned int uiRndSeedInit; // Dither random seed initial value
asrc_state_t* unsafe psState; // Pointer to state structure
int* unsafe piStack; // Pointer to stack buffer
int* unsafe piADCoefs; // Pointer to AD coefficients
#else
long long pad_to_64b_alignment; //Force compiler to 64b align
unsigned int uiNchannels; // Number of channels in this instance
int* piIn; // Input buffer pointer (PCM, 32bits, 2 channels time domain interleaved data)
unsigned int uiNInSamples; // Number of input samples to process in one call to the processing function
unsigned int uiNSyncSamples; // Number of synchronous samples produced in one call to the processing function
ASRCFs_t eInFs; // Input sampling rate code
int* piOut; // Output buffer poin ter (PCM, 32bits, 2 channels time domain interleaved data)
unsigned int uiNASRCOutSamples; // Number of output samples produced during last call to the asynchronous processing function
ASRCFs_t eOutFs; // Output sampling rate code
FIRCtrl_t sFIRF1Ctrl; // F1 FIR controller
FIRCtrl_t sFIRF2Ctrl; // F2 FIR controller
ADFIRCtrl_t sADFIRF3Ctrl; // F3 ADFIR controller
unsigned int uiFsRatio; // Fs ratio: Fsin / Fsout
unsigned int uiFsRatio_lo;
int iTimeInt; // Integer part of time
unsigned int uiTimeFract; // Fractional part of time
int iTimeStepInt; // Integer part of time step
unsigned int uiTimeStepFract; // Fractional part of time step
unsigned int uiDitherOnOff; // Dither on/off flag
unsigned int uiRndSeedInit; // Dither random seed initial value
asrc_state_t* psState; // Pointer to state structure
int* piStack; // Pointer to stack buffer
int* piADCoefs; // Pointer to AD coefficients
#endif
} asrc_ctrl_t;
// Adaptive filter coefficients. Note this is a workaround to force the compiler to align the array to 64b boundary (required by inner loop assembler that uses load/store double)
// -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
typedef struct _asrc_adfir_coefs_t
{
long long padding_to_64b; //Force 64b alignment
int iASRCADFIRCoefs[ASRC_ADFIR_COEFS_LENGTH]; //Adaptive FIR coefficients (one per instance)
} asrc_adfir_coefs_t;
// ===========================================================================
//
// Function prototypes
//
// ===========================================================================
// ==================================================================== //
// Function: ASRC_prepare_coefs //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Prepares the ASRC coefficients from the prototype //
// Needs to be called only once //
// ==================================================================== //
ASRCReturnCodes_t ASRC_prepare_coefs(void);
// ==================================================================== //
// Function: ASRC_init //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Inits the ASRC passed as argument //
// ==================================================================== //
ASRCReturnCodes_t ASRC_init(asrc_ctrl_t* pasrc_ctrl);
// ==================================================================== //
// Function: ASRC_sync //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Syncs the ASRC passed as argument //
// ==================================================================== //
ASRCReturnCodes_t ASRC_sync(asrc_ctrl_t* pasrc_ctrl);
// ==================================================================== //
// Function: ASRC_proc_F1_F2 //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Processes F1 and F2 for a channel //
// ==================================================================== //
ASRCReturnCodes_t ASRC_proc_F1_F2(asrc_ctrl_t* pasrc_ctrl);
// ==================================================================== //
// Function: ASRC_update_fs_ratio //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Updates the ASRC with the new Fs ratio //
// ==================================================================== //
ASRCReturnCodes_t ASRC_update_fs_ratio(asrc_ctrl_t* pasrc_ctrl);
// ==================================================================== //
// Function: ASRC_proc_F3_in_spl //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// int iInSample: new input sample //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Writes new input sample to F3 delay line //
// ==================================================================== //
ASRCReturnCodes_t ASRC_proc_F3_in_spl(asrc_ctrl_t* pasrc_ctrl, int iInSample);
// ==================================================================== //
// Function: ASRC_proc_F3_time //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR if an output sample must be produced //
// ASRC_ERROR if no output sample needs to be produced //
// Description: Processes F3 time //
// ==================================================================== //
ASRCReturnCodes_t ASRC_proc_F3_time(asrc_ctrl_t* pasrc_ctrl);
// ==================================================================== //
// Function: ASRC_proc_F3_macc //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// int* piOutSample: Address of output sample //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Processes F3 for a channel //
// ==================================================================== //
ASRCReturnCodes_t ASRC_proc_F3_macc(asrc_ctrl_t* pasrc_ctrl, int* piOutSample);
// ==================================================================== //
// Function: ASRC_proc_dither //
// Arguments: asrc_ctrl_t *pasrc_ctrl: Ctrl strct. //
// Return values: ASRC_NO_ERROR on success //
// ASRC_ERROR on failure //
// Description: Processes dither for a channel //
// ==================================================================== //
ASRCReturnCodes_t ASRC_proc_dither(asrc_ctrl_t* pasrc_ctrl);
#endif // nINCLUDE_FROM_ASM
#endif // _SRC_MRHF_ASRC_H_

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// Copyright 2016-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _SRC_MRHF_ASRC_CHECKS_H_
#define _SRC_MRHF_ASRC_CHECKS_H_
#include "src.h"
//Compile time checks on SRC configuration defines
#if (ASRC_N_CHANNELS % ASRC_N_INSTANCES != 0)
#error "Each core must process an integer number of channels. Check ASRC_N_CHANNELS & ASRC_N_INSTANCES."
#endif
#if (ASRC_N_CHANNELS < ASRC_N_INSTANCES)
#error "Each instance (logical core) must process at least one channel. Check ASRC_N_CHANNELS & ASRC_N_INSTANCES."
#endif
#if (ASRC_N_INSTANCES < 1)
#error "Number of instances (logical cores) must be at least 1. Check ASRC_N_INSTANCES."
#endif
#if (ASRC_N_CHANNELS < 1)
#error "Number of audio channels must be at least 1. Check ASRC_N_CHANNELS."
#endif
#if (ASRC_N_IN_SAMPLES < 4)
#error "Number of input audio samples in each block must be at least 4. Check ASRC_N_IN_SAMPLES."
#endif
#if ((ASRC_N_IN_SAMPLES & (ASRC_N_IN_SAMPLES - 1)) != 0)
#error "Number of input audio samples in each block must be a power of two. Check ASRC_N_IN_SAMPLES."
#endif
#if (ASRC_N_OUT_IN_RATIO_MAX < 5)
#warning "SRC buffering configured so that fs out <= 4 * fs in"
#endif
#if (ASRC_N_OUT_IN_RATIO_MAX < 3)
#warning "SRC buffering configured so that fs out <= 2 * fs in"
#endif
#if (ASRC_N_OUT_IN_RATIO_MAX < 1)
#warning "SRC buffering configured so that fs out <= fs in"
#endif
#endif // _SRC_MRHF_ASRC_CHECKS_H_

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// Copyright 2016-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
// General includes
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
#include <timer.h>
#include "debug_print.h"
// ASRC includes
#include "src.h"
#include "use_vpu.h"
extern ASRCFsRatioConfigs_t sFsRatioConfigs[ASRC_N_FS][ASRC_N_FS];
#define DO_FS_BOUNDS_CHECK 1 //This is important to prevent pointers going out of bounds when invalid fs_ratios are sent
static void asrc_error(int code)
{
debug_printf("ASRC_proc Error code %d\n", code);
delay_milliseconds(1); //Allow xscope to display message before quit
_Exit(code);
}
uint64_t asrc_init(const fs_code_t sr_in, const fs_code_t sr_out, asrc_ctrl_t asrc_ctrl[], const unsigned n_channels_per_instance,
const unsigned n_in_samples, const dither_flag_t dither_on_off)
{
unsigned ui;
ASRCReturnCodes_t ret_code;
ret_code = ASRC_prepare_coefs();
if (ret_code != ASRC_NO_ERROR) asrc_error(10);
//Check to see if n_channels_per_instance, n_in_samples are reasonable
if ((n_in_samples & 0x1) || (n_in_samples < 4)) asrc_error(100);
if (n_channels_per_instance < 1) asrc_error(101);
for(ui = 0; ui < n_channels_per_instance; ui++)
{
// Set number of channels per instance
asrc_ctrl[ui].uiNchannels = n_channels_per_instance;
// Set input/output sampling rate codes
asrc_ctrl[ui].eInFs = (int)sr_in;
asrc_ctrl[ui].eOutFs = (int)sr_out;
// Set number of samples
asrc_ctrl[ui].uiNInSamples = n_in_samples;
// Set dither flag and random seeds
asrc_ctrl[ui].uiDitherOnOff = dither_on_off;
asrc_ctrl[ui].uiRndSeedInit = 12345 * ui; //Some randomish numbers. Value not critical
// Init ASRC instances
ret_code = ASRC_init(&asrc_ctrl[ui]);
if (ret_code != ASRC_NO_ERROR) asrc_error(11);
}
// Sync
// ----
// Sync ASRC. This is just to show that the function works and returns success
for(ui = 0; ui < n_channels_per_instance; ui++) {
ret_code = ASRC_sync(&asrc_ctrl[ui]);
if (ret_code != ASRC_NO_ERROR) asrc_error(12);
}
return (uint64_t)((((uint64_t)asrc_ctrl[0].uiFsRatio) << 32) | asrc_ctrl[0].uiFsRatio_lo);
}
unsigned asrc_process(int *in_buff, int *out_buff, uint64_t fs_ratio, asrc_ctrl_t asrc_ctrl[]){
int ui, uj; //General counters
int uiSplCntr; //Spline counter
// Get the number of channels per instance from first channel
const unsigned n_channels_per_instance = asrc_ctrl[0].uiNchannels;
uint32_t fs_ratio_hi = (uint32_t)(fs_ratio >> 32);
uint32_t fs_ratio_lo = (uint32_t)(fs_ratio);
for(ui = 0; ui < n_channels_per_instance; ui++)
{
// Update Fs Ratio
asrc_ctrl[ui].uiFsRatio = fs_ratio_hi;
asrc_ctrl[ui].uiFsRatio_lo = fs_ratio_lo;
#if DO_FS_BOUNDS_CHECK
// Check for bounds of new Fs ratio
if( (fs_ratio_hi < sFsRatioConfigs[asrc_ctrl[ui].eInFs][asrc_ctrl[ui].eOutFs].uiMinFsRatio) ||
(fs_ratio_hi > sFsRatioConfigs[asrc_ctrl[ui].eInFs][asrc_ctrl[ui].eOutFs].uiMaxFsRatio) )
{
//debug_printf("Passed = %x, Nominal = 0x%x\n", fs_ratio_hi, sFsRatioConfigs[asrc_ctrl[ui].eInFs][asrc_ctrl[ui].eOutFs].uiNominalFsRatio);
fs_ratio_hi = sFsRatioConfigs[asrc_ctrl[ui].eInFs][asrc_ctrl[ui].eOutFs].uiNominalFsRatio; //Important to prevent buffer overflow if fs_ratio requests too many samples.
fs_ratio_lo = sFsRatioConfigs[asrc_ctrl[ui].eInFs][asrc_ctrl[ui].eOutFs].uiNominalFsRatio_lo;
//debug_printf("!");
}
#endif
// Apply shift to time ratio to build integer and fractional parts of time step
asrc_ctrl[ui].iTimeStepInt = fs_ratio_hi >> (sFsRatioConfigs[asrc_ctrl[ui].eInFs][asrc_ctrl[ui].eOutFs].iFsRatioShift);
asrc_ctrl[ui].uiTimeStepFract = fs_ratio_hi << (32 - sFsRatioConfigs[asrc_ctrl[ui].eInFs][asrc_ctrl[ui].eOutFs].iFsRatioShift);
asrc_ctrl[ui].uiTimeStepFract |= (uint32_t)(fs_ratio_lo >> sFsRatioConfigs[asrc_ctrl[ui].eInFs][asrc_ctrl[ui].eOutFs].iFsRatioShift);
// Set input and output data pointers
asrc_ctrl[ui].piIn = in_buff + ui;
asrc_ctrl[ui].piOut = out_buff + ui;
// Process synchronous part (F1 + F2)
// ==================================
// Note: this is block based similar to SSRC, output will be on stack
// and there will be asrc_ctrl[chan_start].uiNSyncSamples samples per channel produced
if(ASRC_proc_F1_F2(&asrc_ctrl[ui]) != ASRC_NO_ERROR)
{
asrc_error(12);
}
// Run the asynchronous part (F3)
// ==============================
// Clear number of output samples (note that this sample counter would actually not be needed if all was sample by sampe)
asrc_ctrl[ui].uiNASRCOutSamples = 0;
}
uiSplCntr = 0; // This is actually only used because of the bizarre mix of block and sample based processing
// Driven by samples produced during the synchronous phase
for(ui = 0; ui < asrc_ctrl[0].uiNSyncSamples; ui++)
{
// Push new samples into F3 delay line (input from stack) for each new "synchronous" sample (i.e. output of F1, respectively F2)
for(uj = 0; uj < n_channels_per_instance; uj++)
{
//The following is replicated/inlined code from ASRC_proc_F3_in_spl in ASRC.c
asrc_ctrl[uj].sADFIRF3Ctrl.iIn = asrc_ctrl[uj].piStack[ui];
//The following is replicated/inlined code from ADFIR_proc_in_spl in FIR.c
// Double write to simulate circular buffer
*asrc_ctrl[uj].sADFIRF3Ctrl.piDelayI = asrc_ctrl[uj].sADFIRF3Ctrl.iIn;
*(asrc_ctrl[uj].sADFIRF3Ctrl.piDelayI + asrc_ctrl[uj].sADFIRF3Ctrl.uiDelayO) = asrc_ctrl[uj].sADFIRF3Ctrl.iIn;
// Step delay (with circular simulation)
asrc_ctrl[uj].sADFIRF3Ctrl.piDelayI++;
if(asrc_ctrl[uj].sADFIRF3Ctrl.piDelayI >= asrc_ctrl[uj].sADFIRF3Ctrl.piDelayW)
asrc_ctrl[uj].sADFIRF3Ctrl.piDelayI =asrc_ctrl[uj].sADFIRF3Ctrl.piDelayB;
// Decrease next output time (this is an integer value, so no influence on fractional part)
asrc_ctrl[uj].iTimeInt -= FILTER_DEFS_ADFIR_N_PHASES;
}
// Run macc loop for F3
// Check if a new output sample needs to be produced
// Note that this will also update the adaptive filter coefficients
// These must be computed for one channel only and reused in the macc loop of other channels
while(asrc_ctrl[0].iTimeInt < FILTER_DEFS_ADFIR_N_PHASES)
{
unsigned int uiTemp;
int iAlpha;
int iH[3]; //iH0, iH1, iH2;
long long i64Acc0;
int* piPhase0;
int* piADCoefs;
// Compute adative coefficients spline factors
// The fractional part of time gives alpha
iAlpha = asrc_ctrl[0].uiTimeFract>>1; // Now alpha can be seen as a signed number
i64Acc0 = (long long)iAlpha * (long long)iAlpha;
#if SRC_USE_VPU
iH[2] = (int)(i64Acc0>>32);
iH[0] = 0x40000000; // Load H2 with 0.5;
iH[1] = iH[0] - iH[2]; // H1 = 0.5 - 0.5 * alpha * alpha;
iH[1] = iH[1] - iH[2]; // H1 = 0.5 - alpha * alpha
iH[1] = iH[1] + iAlpha; // H1 = 0.5 + alpha - alpha * alpha;
iH[0] = iH[0] - iAlpha; // H2 = 0.5 - alpha
iH[0] = iH[0] + iH[2]; // H2 = 0.5 - alpha + 0.5 * alpha * alpha
// The integer part of time gives the phase
piPhase0 = &iADFirCoefs[0][asrc_ctrl[0].iTimeInt];
// These are calculated by the asm funcion piPhase1 = piPhase0 + FILTER_DEFS_ADFIR_PHASE_N_TAPS;
// piPhase2 = piPhase1 + FILTER_DEFS_ADFIR_PHASE_N_TAPS;
piADCoefs = asrc_ctrl[0].piADCoefs; // Given limited number of registers, this could be DP
// Apply spline coefficients to filter coefficients
src_mrhf_spline_coeff_gen_inner_loop_asm_xs3(piPhase0, iH, piADCoefs, FILTER_DEFS_ADFIR_PHASE_N_TAPS);
#else
iH[0] = (int)(i64Acc0>>32);
iH[2] = 0x40000000; // Load H2 with 0.5;
iH[1] = iH[2] - iH[0]; // H1 = 0.5 - 0.5 * alpha * alpha;
iH[1] = iH[1] - iH[0]; // H1 = 0.5 - alpha * alpha
iH[1] = iH[1] + iAlpha; // H1 = 0.5 + alpha - alpha * alpha;
iH[2] = iH[2] - iAlpha; // H2 = 0.5 - alpha
iH[2] = iH[2] + iH[0]; // H2 = 0.5 - alpha + 0.5 * alpha * alpha
// The integer part of time gives the phase
piPhase0 = iADFirCoefs[asrc_ctrl[0].iTimeInt];
// These are calculated by the asm funcion piPhase1 = piPhase0 + FILTER_DEFS_ADFIR_PHASE_N_TAPS;
// piPhase2 = piPhase1 + FILTER_DEFS_ADFIR_PHASE_N_TAPS;
piADCoefs = asrc_ctrl[0].piADCoefs; // Given limited number of registers, this could be DP
// Apply spline coefficients to filter coefficients
src_mrhf_spline_coeff_gen_inner_loop_asm(piPhase0, iH, piADCoefs, FILTER_DEFS_ADFIR_PHASE_N_TAPS);
#endif
// Step time for next output sample
// --------------------------------
// Step to next output time (add integer and fractional parts)
asrc_ctrl[0].iTimeInt += asrc_ctrl[0].iTimeStepInt;
// For fractional part, this can be optimized using the add with carry instruction of XS2
uiTemp = asrc_ctrl[0].uiTimeFract;
asrc_ctrl[0].uiTimeFract += asrc_ctrl[0].uiTimeStepFract;
if(asrc_ctrl[0].uiTimeFract < uiTemp)
asrc_ctrl[0].iTimeInt++;
// Not really needed, just for the beauty of it...
//asrc_ctrl[0+1].iTimeInt = asrc_ctrl[0].iTimeInt;
//asrc_ctrl[0+1].uiTimeFract = asrc_ctrl[0].uiTimeFract;
// Apply filter F3 with just computed adaptive coefficients
for(uj = 0; uj < n_channels_per_instance; uj++) {
//The following is replicated/inlined code from ADFIR_F3_proc_macc in ASRC.c
asrc_ctrl[uj].sADFIRF3Ctrl.piOut = (asrc_ctrl[uj].piOut + n_channels_per_instance * uiSplCntr);
//The following is replicated/inlined code from ADFIR_proc_macc in FIR.c
int* piData;
int* piCoefs;
int iData;
// Clear accumulator and set access pointers
piData = asrc_ctrl[uj].sADFIRF3Ctrl.piDelayI;
piCoefs = asrc_ctrl[uj].sADFIRF3Ctrl.piADCoefs;
// Do FIR
#if SRC_USE_VPU
src_mrhf_adfir_inner_loop_asm_xs3(piData, piCoefs, &iData, asrc_ctrl[uj].sADFIRF3Ctrl.uiNLoops);
#else
if ((unsigned)piData & 0b0100) src_mrhf_adfir_inner_loop_asm_odd(piData, piCoefs, &iData, asrc_ctrl[uj].sADFIRF3Ctrl.uiNLoops);
else src_mrhf_adfir_inner_loop_asm(piData, piCoefs, &iData, asrc_ctrl[uj].sADFIRF3Ctrl.uiNLoops);
#endif
// Write output
*(asrc_ctrl[uj].sADFIRF3Ctrl.piOut) = iData;
asrc_ctrl[uj].uiNASRCOutSamples++;
}
uiSplCntr++; // This is actually only used because of the bizarre mix of block and sample based processing
}
}
#if (ASRC_DITHER_SETTING != ASRC_DITHER_OFF) //Removed for speed optimisation
// Process dither part
// ===================
// We are back to block based processing. This is where the number of ASRC output samples is required again
// (would not be used if sample by sample based (on output samples))
for(ui = 0; ui < n_channels_per_instance; ui++)
{
// Note: this is block based similar to SSRC
if(ASRC_proc_dither(&asrc_ctrl[ui]) != ASRC_NO_ERROR)
{
asrc_error(4);
}
}
#endif
unsigned n_samps_out = asrc_ctrl[0].uiNASRCOutSamples;
return n_samps_out;
}

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// Copyright 2016-2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
.section .dp.data,"awd",@progbits
.text
.cc_top src_mrhf_adfir_inner_loop_asm.function
.globl src_mrhf_adfir_inner_loop_asm
.align 8
.type src_mrhf_adfir_inner_loop_asm,@function
src_mrhf_adfir_inner_loop_asm:
#define piData_p r0
#define piCoefs_p r1
#define iDataRet_p r2
#define step r2
#define counter r3
#define iCoef0 r4
#define iCoef1 r5
#define iData0 r6
#define iData1 r7
#define Acc0_l r8
#define Acc0_h r9
//In 32b words
#define stack_size 8
.issue_mode dual
//Push registers
DUALENTSP_lu6 stack_size
std r4, r5, sp[0]
std r6, r7, sp[1]
std r8, r9, sp[2]
//push return value pointers onto stack. Frees up r2
//Divide counter by 8
{stw iDataRet_p, sp[6]; shr counter, counter, 3}
//Constant for adding onto stuff. Gets updated later
ldc step, 0x40
//Initilise MACC regsiters to zero
{ldc Acc0_h, 0; ldc Acc0_l, 0}
bf counter, src_mrhf_adfir_done
src_mrhf_adfir_main_loop:
sub counter, counter, 1
ldd iData0, iData1, piData_p[0]
ldd iCoef0, iCoef1, piCoefs_p[0]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[1]
ldd iCoef0, iCoef1, piCoefs_p[1]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[2]
ldd iCoef0, iCoef1, piCoefs_p[2]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[3]
ldd iCoef0, iCoef1, piCoefs_p[3]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[4]
ldd iCoef0, iCoef1, piCoefs_p[4]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[5]
ldd iCoef0, iCoef1, piCoefs_p[5]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[6]
ldd iCoef0, iCoef1, piCoefs_p[6]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iData0, iData1, piData_p[7]
ldd iCoef0, iCoef1, piCoefs_p[7]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
//Decrement loop counter and increment pointers and branch if still running
{add piData_p, piData_p, step; add piCoefs_p, piCoefs_p, step}
bt counter, src_mrhf_adfir_main_loop
src_mrhf_adfir_done:
//pop return value pointer from stack so we can use it to write back
//Write back the two return values
{ldw iDataRet_p, sp[6]; ldc counter, 30} //Reuse counter (r3)
lsats Acc0_h, Acc0_l, r3 //Saturate first
lextract iData0, Acc0_h, Acc0_l, counter, 32 //Extract
stw iData0, iDataRet_p[0]
//Pop registers
ldd r4, r5, sp[0]
ldd r6, r7, sp[1]
ldd r8, r9, sp[2]
retsp stack_size
.atmp:
.size src_mrhf_adfir_inner_loop_asm, .atmp-src_mrhf_adfir_inner_loop_asm
.align 8
.cc_bottom src_mrhf_adfir_inner_loop_asm.function
.set src_mrhf_adfir_inner_loop_asm.nstackwords, stack_size
.globl src_mrhf_adfir_inner_loop_asm.nstackwords
.set src_mrhf_adfir_inner_loop_asm.maxcores, 1
.globl src_mrhf_adfir_inner_loop_asm.maxcores
.set src_mrhf_adfir_inner_loop_asm.maxtimers,0
.globl src_mrhf_adfir_inner_loop_asm.maxtimers
.set src_mrhf_adfir_inner_loop_asm.maxchanends,0
.globl src_mrhf_adfir_inner_loop_asm.maxchanends
// Odd data alignment (4byte odd instead of 8byte) version
.section .dp.data,"awd",@progbits
.text
.cc_top src_mrhf_adfir_inner_loop_asm_odd.function
.globl src_mrhf_adfir_inner_loop_asm_odd
.align 8
.type src_mrhf_adfir_inner_loop_asm_odd,@function
src_mrhf_adfir_inner_loop_asm_odd:
#define piData_p r0
#define piCoefs_p r1
#define iDataRet_p r2
#define step r2
#define counter r3
#define iCoef0 r4
#define iCoef1 r5
#define iData0 r6
#define iData1 r7
#define Acc0_l r8
#define Acc0_h r9
//In 32b words
#define stack_size 8
.issue_mode dual
//Push registers
DUALENTSP_lu6 stack_size
std r4, r5, sp[0]
std r6, r7, sp[1]
std r8, r9, sp[2]
//push return value pointers onto stack. Frees up r2
//Divide counter by 8
{stw iDataRet_p, sp[6]; shr counter, counter, 3}
//Initilise MACC regsiters to zero
{ldc Acc0_h, 0; ldc Acc0_l, 0}
bf counter, src_mrhf_adfir_done_odd
src_mrhf_adfir_main_loop_odd:
{sub counter, counter, 1; ldc step, 0x38}
//Constant for adding onto stuff. Gets updated later
{ldw iData0, piData_p[0]; add piData_p, piData_p, 4} //Now 64b aligned
ldd iCoef1, iCoef0, piCoefs_p[0]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[0]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[1]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[1]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[2]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[2]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[3]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[3]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[4]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[4]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[5]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[5]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[6]
maccs Acc0_h, Acc0_l, iData0, iCoef0
ldd iData0, iData1, piData_p[6]
maccs Acc0_h, Acc0_l, iData1, iCoef1
ldd iCoef1, iCoef0, piCoefs_p[7]
maccs Acc0_h, Acc0_l, iData0, iCoef0
add piData_p, piData_p, step
{ldw iData1, piData_p[0]; add piData_p, piData_p, 4} //0x4 + 0x38 + 0x4 = 0x40)
maccs Acc0_h, Acc0_l, iData1, iCoef1
//Increment pointers and branch if still running
ldc step, 0x40
{bt counter, src_mrhf_adfir_main_loop_odd; add piCoefs_p, piCoefs_p, step}
src_mrhf_adfir_done_odd:
//pop return value pointer from stack so we can use it to write back
{ldw iDataRet_p, sp[6]; ldc counter, 30} //Reuse counter (r3)
//Write back the return value
lsats Acc0_h, Acc0_l, r3 //Saturate first
lextract iData0, Acc0_h, Acc0_l, counter, 32 //Extract
stw iData0, iDataRet_p[0]
//Pop registers
ldd r4, r5, sp[0]
ldd r6, r7, sp[1]
ldd r8, r9, sp[2]
retsp stack_size
.atmp_odd:
.size src_mrhf_adfir_inner_loop_asm_odd, .atmp_odd-src_mrhf_adfir_inner_loop_asm_odd
.align 8
.cc_bottom src_mrhf_adfir_inner_loop_asm_odd.function
.set src_mrhf_adfir_inner_loop_asm_odd.nstackwords, stack_size
.globl src_mrhf_adfir_inner_loop_asm_odd.nstackwords
.set src_mrhf_adfir_inner_loop_asm_odd.maxcores, 1
.globl src_mrhf_adfir_inner_loop_asm_odd.maxcores
.set src_mrhf_adfir_inner_loop_asm_odd.maxtimers,0
.globl src_mrhf_adfir_inner_loop_asm_odd.maxtimers
.set src_mrhf_adfir_inner_loop_asm_odd.maxchanends,0
.globl src_mrhf_adfir_inner_loop_asm_odd.maxchanends

10
lib_src/lib_src/src/multirate_hifi/src_mrhf_adfir_inner_loop_asm.h Normal file
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// Copyright 2016-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#ifndef _SRC_MRHF_ADFIR_INNER_LOOP_ASM_H_
#define _SRC_MRHF_ADFIR_INNER_LOOP_ASM_H_
void src_mrhf_adfir_inner_loop_asm(int *piData, int *piCoefs, int iData[], int count);
void src_mrhf_adfir_inner_loop_asm_odd(int *piData, int *piCoefs, int iData[], int count);
void src_mrhf_adfir_inner_loop_asm_xs3(int *piData, int *piCoefs, int iData[], int count);
#endif // _SRC_MRHF_ADFIR_INNER_LOOP_ASM_H_

241
lib_src/lib_src/src/multirate_hifi/src_mrhf_adfir_inner_loop_asm_xs3.S Normal file
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// Copyright 2016-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#if defined(__XS3A__)
.text
#define NSTACKWORDS 8
.issue_mode dual
.align 16
.cc_top src_mrhf_adfir_inner_loop_asm_xs3.function
.globl src_mrhf_adfir_inner_loop_asm_xs3
.type src_mrhf_adfir_inner_loop_asm_xs3,@function
src_mrhf_adfir_inner_loop_asm_xs3:
{ DUALENTSP_u6 NSTACKWORDS ; ldc r11, 0 }
{ vsetc r11 ; shr r3, r3, 3}
{ ldc r11, 0x20 ; vclrdr }
{ bf r3, src_mrhf_adfir_done2 ; sub r3, r3, 1 }
src_mrhf_adfir_main_loop2:
{ vldc r0[0] ; add r0, r0, r11 }
{ vlmaccr r1[0] ; add r1, r1, r11 }
{ vldc r0[0] ; add r0, r0, r11 }
{ vlmaccr r1[0] ; add r1, r1, r11 }
{ bt r3, src_mrhf_adfir_main_loop2 ; sub r3, r3, 1 }
src_mrhf_adfir_done2:
ldap r11, shifts1
{ vlsat r11[0] ; ldaw r0, sp[0] }
vstr r0[0]
{ vldc r0[0] ; ldap r11, twos }
vclrdr
{ vlmaccr r11[0] ; ldap r11, shifts0 }
{ vlsat r11[0] ; mkmsk r0, 4 }
vstrpv r2[0], r0
retsp NSTACKWORDS
.atmp:
.size src_mrhf_adfir_inner_loop_asm_xs3, .atmp-src_mrhf_adfir_inner_loop_asm_xs3
.set src_mrhf_adfir_inner_loop_asm_xs3.nstackwords, NSTACKWORDS
.globl src_mrhf_adfir_inner_loop_asm_xs3.nstackwords
.set src_mrhf_adfir_inner_loop_asm_xs3.maxcores, 1
.globl src_mrhf_adfir_inner_loop_asm_xs3.maxcores
.set src_mrhf_adfir_inner_loop_asm_xs3.maxtimers,0
.globl src_mrhf_adfir_inner_loop_asm_xs3.maxtimers
.set src_mrhf_adfir_inner_loop_asm_xs3.maxchanends,0
.globl src_mrhf_adfir_inner_loop_asm_xs3.maxchanends
.globl src_mrhf_fir_inner_loop_asm_xs3
.type src_mrhf_fir_inner_loop_asm_xs3,@function
#undef NSTACKWORDS
#define NSTACKWORDS 8
twos:
.word 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff
.word 0x7fffffff, 0x7fffffff, 0x7fffffff, 0x7fffffff
shifts0:
.word 0, 0, 0, 0, 0, 0, 0, 0
shifts1:
.word 1, 1, 1, 1, 1, 1, 1, 1
shifts2:
.word 2, 2, 2, 2, 2, 2, 2, 2
.align 16
src_mrhf_fir_inner_loop_asm_xs3:
{ DUALENTSP_u6 NSTACKWORDS ; ldc r11, 0 }
{ vsetc r11 ; shr r3, r3, 3}
{ ldc r11, 0x20 ; vclrdr }
{ bf r3, src_mrhf_fir_done2 ; sub r3, r3, 1 }
src_mrhf_fir_main_loop2:
{ vldc r0[0] ; add r0, r0, r11 }
{ vlmaccr r1[0] ; add r1, r1, r11 }
{ vldc r0[0] ; add r0, r0, r11 }
{ vlmaccr r1[0] ; add r1, r1, r11 }
{ bt r3, src_mrhf_fir_main_loop2 ; sub r3, r3, 1 }
src_mrhf_fir_done2:
ldap r11, shifts2
{ vlsat r11[0] ; ldaw r0, sp[0] }
vstr r0[0]
{ vldc r0[0] ; ldap r11, twos }
vclrdr
{ vlmaccr r11[0] ; ldap r11, shifts0 }
{ vlsat r11[0] ; mkmsk r0, 4 }
vstrpv r2[0], r0
retsp NSTACKWORDS
.btmp:
.size src_mrhf_fir_inner_loop_asm_xs3, .btmp-src_mrhf_fir_inner_loop_asm_xs3
.set src_mrhf_fir_inner_loop_asm_xs3.nstackwords, NSTACKWORDS
.globl src_mrhf_fir_inner_loop_asm_xs3.nstackwords
.set src_mrhf_fir_inner_loop_asm_xs3.maxcores, 1
.globl src_mrhf_fir_inner_loop_asm_xs3.maxcores
.set src_mrhf_fir_inner_loop_asm_xs3.maxtimers,0
.globl src_mrhf_fir_inner_loop_asm_xs3.maxtimers
.set src_mrhf_fir_inner_loop_asm_xs3.maxchanends,0
.globl src_mrhf_fir_inner_loop_asm_xs3.maxchanends
.globl src_mrhf_fir_os_inner_loop_asm_xs3
.type src_mrhf_fir_os_inner_loop_asm_xs3,@function
#undef NSTACKWORDS
#define NSTACKWORDS 8
evens:
.word 0x7fffffff
odds:
.word 0, 0x7fffffff, 0, 0x7fffffff, 0, 0x7fffffff, 0, 0x7fffffff
.align 16
src_mrhf_fir_os_inner_loop_asm_xs3:
{ DUALENTSP_u6 NSTACKWORDS ; ldc r11, 0x0 }
{ vsetc r11 ; shr r3, r3, 2 }
{ ldc r11, 0x20 ; vclrdr }
{ bf r3, src_mrhf_fir_os_done2 ; sub r3, r3, 1 }
src_mrhf_fir_os_main_loop2:
{ vldc r0[0] ; add r0, r0, r11 }
{ vlmaccr r1[0] ; add r1, r1, r11 }
{ vlmaccr r1[0] ; add r1, r1, r11 }
//Decrement loop r3
{ bt r3, src_mrhf_fir_os_main_loop2 ; sub r3, r3, 1 }
src_mrhf_fir_os_done2:
ldap r11, shifts2
{ vlsat r11[0] ; ldaw r0, sp[0] }
vstr r0[0]
{ vldc r0[0] ; ldap r11, evens }
vclrdr
{ vlmaccr r11[0] ; add r11, r11, 4 }
{ vlmaccr r11[0] ; ldap r11, shifts0 }
{ vlsat r11[0] ; mkmsk r0, 8 }
vstrpv r2[0], r0
//Pop registers
retsp NSTACKWORDS
.ctmp:
.size src_mrhf_fir_os_inner_loop_asm_xs3, .ctmp-src_mrhf_fir_os_inner_loop_asm_xs3
.set src_mrhf_fir_os_inner_loop_asm_xs3.nstackwords, NSTACKWORDS
.globl src_mrhf_fir_os_inner_loop_asm_xs3.nstackwords
.set src_mrhf_fir_os_inner_loop_asm_xs3.maxcores, 1
.globl src_mrhf_fir_os_inner_loop_asm_xs3.maxcores
.set src_mrhf_fir_os_inner_loop_asm_xs3.maxtimers,0
.globl src_mrhf_fir_os_inner_loop_asm_xs3.maxtimers
.set src_mrhf_fir_os_inner_loop_asm_xs3.maxchanends,0
.globl src_mrhf_fir_os_inner_loop_asm_xs3.maxchanends
#define FILTER_DEFS_ADFIR_N_PHASES 128
.globl src_mrhf_spline_coeff_gen_inner_loop_asm_xs3
.align 16
.type src_mrhf_spline_coeff_gen_inner_loop_asm_xs3,@function
#undef NSTACKWORDS
#define NSTACKWORDS 8
src_mrhf_spline_coeff_gen_inner_loop_asm_xs3:
DUALENTSP_lu6 NSTACKWORDS
ldc r3, (FILTER_DEFS_ADFIR_N_PHASES + 2)<< 2
// p0, p1, p2, p3, ..., p15
// p0+N, p1+N, p2+N, ....,p15+N
// p0+2N, p1+2N, p2+2N, ....,p15+2N
// p0+3N, p1+3N, p2+3N, ....,p15+3N
// ...
// p0+257N, p1+257N, p2+257N, ....,p15+257N
// ****
// p0, p0+N, p0+2N, ...., p0+257N
// p1, p1+N, p1+2N, ...., p1+257N
// ...
// a0 = p[0] * H[2] + p[0+N] * H[1] * p[0+2N] * H[0]
// a1 = p[1] * H[2] + p[1+N] * H[1] * p[1+2N] * H[0]
// a2 = p[2] * H[2] + p[2+N] * H[1] * p[2+2N] * H[0]
// a3 = p[3] * H[2] + p[3+N] * H[1] * p[3+2N] * H[0]
// Ensure that H is padded with five zeroes.
// There may be a faster way to achieve this with VLMUL
{ vldd r1[0] ; ldaw r1, sp[0] }
{ vstd r1[0] ; ldc r11, 0 }
vsetc r11
stw r11, sp[3]
std r11, r11, sp[2]
std r11, r11, sp[3]
src_mrhf_spline_coeff_gen_main_loop2:
{ vclrdr ; ldap r11, shifts2 }
vldc r1[0]
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
vlsat r11[0]
vstr r2[0]
ldaw r2, r2[8]
vclrdr
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
{ vlmaccr r0[0] ; add r0, r0, r3 }
vlsat r11[0]
vstr r2[0]
src_mrhf_spline_coeff_gen_done2:
retsp NSTACKWORDS
.dtmp:
.size src_mrhf_spline_coeff_gen_inner_loop_asm_xs3, .dtmp-src_mrhf_spline_coeff_gen_inner_loop_asm_xs3
.cc_bottom src_mrhf_adfir_inner_loop_asm_xs3.function
.set src_mrhf_spline_coeff_gen_inner_loop_asm_xs3.nstackwords, NSTACKWORDS
.globl src_mrhf_spline_coeff_gen_inner_loop_asm_xs3.nstackwords
.set src_mrhf_spline_coeff_gen_inner_loop_asm_xs3.maxcores, 1
.globl src_mrhf_spline_coeff_gen_inner_loop_asm_xs3.maxcores
.set src_mrhf_spline_coeff_gen_inner_loop_asm_xs3.maxtimers,0
.globl src_mrhf_spline_coeff_gen_inner_loop_asm_xs3.maxtimers
.set src_mrhf_spline_coeff_gen_inner_loop_asm_xs3.maxchanends,0
.globl src_mrhf_spline_coeff_gen_inner_loop_asm_xs3.maxchanends
#endif

73
lib_src/lib_src/src/multirate_hifi/src_mrhf_dither_maths_asm.S Normal file
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// Copyright 2016-2021 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
.section .dp.data,"awd",@progbits
.text
.cc_top dither_maths_asm.function
.globl dither_maths_asm
.align 8
.type dither_maths_asm,@function
dither_maths_asm:
#define piData r0
#define ACCh r1
#define ACCl r2
//In 32b words
#define stack_size 0
#if 0
.issue_mode dual
//Push registers
DUALENTSP_lu6 stack_size
std r4, r5, sp[0]
std r6, r7, sp[1]
std r8, r9, sp[2]
//push return value pointers onto stack. Frees up r2
//Divide counter by 8
{stw iDataRet_p, sp[6]; shr counter, counter, 3}
//Constant for adding onto stuff. Gets updated later
ldc step, 0x40
//Initilise MACC regsiters to zero
{ldc Acc0_h, 0; ldc Acc0_l, 0}
ldd iData0, iData1, piData_p[0]
ldd iCoef0, iCoef1, piCoefs_p[0]
maccs Acc0_h, Acc0_l, iData0, iCoef0
maccs Acc0_h, Acc0_l, iData1, iCoef1
//pop return value pointer from stack so we can use it to write back
//Write back the two return values
{ldw iDataRet_p, sp[6]; ldc counter, 31} //Reuse counter (r3)
lsats Acc0_h, Acc0_l, r3 //Saturate first
lextract iData0, Acc0_h, Acc0_l, counter, 32 //Extract
stw iData0, iDataRet_p[0]
//Pop registers
ldd r4, r5, sp[0]
ldd r6, r7, sp[1]
ldd r8, r9, sp[2]
retsp stack_size
#endif
.atmp:
.size dither_maths_asm, .atmp-dither_maths_asm
.align 8
.cc_bottom dither_maths_asm.function
.set dither_maths_asm.nstackwords, stack_size
.globl dither_maths_asm.nstackwords
.set dither_maths_asm.maxcores, 1
.globl dither_maths_asm.maxcores
.set dither_maths_asm.maxtimers,0
.globl dither_maths_asm.maxtimers
.set dither_maths_asm.maxchanends,0
.globl dither_maths_asm.maxchanends

167
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// Copyright 2016-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
// ===========================================================================
// ===========================================================================
//
// Filters Definitions implementation file for the SRC
//
// ===========================================================================
// ===========================================================================
// ===========================================================================
//
// Includes
//
// ===========================================================================
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>
// FIR and FilterDefs includes
#include "src_mrhf_fir.h"
#include "src_mrhf_filter_defs.h"
// ===========================================================================
//
// Defines
//
// ===========================================================================
// ===========================================================================
//
// Variables
//
// ===========================================================================
// SSRC FIR filters descriptors (ordered by ID)
FIRDescriptor_t sSSRCFirDescriptor[FILTER_DEFS_SSRC_N_FIR_ID] =
{
{FIR_TYPE_DS2, FILTER_DEFS_FIR_BL_N_TAPS, iFirBLCoefs}, // FILTER_DEFS_FIR_BL_ID
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BL9644_N_TAPS, iFirBL9644Coefs}, // FILTER_DEFS_FIR_BL9644_ID
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BL8848_N_TAPS, iFirBL8848}, // FILTER_DEFS_FIR_BL8848_ID
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BL19288_N_TAPS, iFirBL19288Coefs}, // FILTER_DEFS_FIR_BL19288_ID
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BL17696_N_TAPS, iFirBL17696}, // FILTER_DEFS_FIR_BL17696_ID
{FIR_TYPE_OS2, FILTER_DEFS_FIR_UP_N_TAPS, iFirUPCoefs}, // FILTER_DEFS_FIR_UP_ID
{FIR_TYPE_OS2, FILTER_DEFS_FIR_UP4844_N_TAPS, iFirUP4844Coefs}, // FILTER_DEFS_FIR_UP4844_ID
{FIR_TYPE_OS2, FILTER_DEFS_FIR_UPF_N_TAPS, iFirUPFCoefs}, // FILTER_DEFS_FIR_UPF_ID
{FIR_TYPE_OS2, FILTER_DEFS_FIR_UP192176_N_TAPS, iFirUP192176Coefs}, // FILTER_DEFS_FIR_UP192176_ID
{FIR_TYPE_DS2, FILTER_DEFS_FIR_DS_N_TAPS, iFirDSCoefs}, // FILTER_DEFS_FIR_DS_ID
{FIR_TYPE_OS2, FILTER_DEFS_FIR_OS_N_TAPS, iFirOSCoefs}, // FILTER_DEFS_FIR_OS_ID
{FIR_TYPE_SYNC, 0, 0} // FILTER_DEFS_FIR_NONE_ID
};
// ASRC FIR filters descriptors (ordered by ID)
FIRDescriptor_t sASRCFirDescriptor[FILTER_DEFS_ASRC_N_FIR_ID] =
{
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BL_N_TAPS, iFirBLCoefs}, // FILTER_DEFS_FIR_BL_ID
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BL9644_N_TAPS, iFirBL9644Coefs}, // FILTER_DEFS_FIR_BL9644_ID
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BL8848_N_TAPS, iFirBL8848}, // FILTER_DEFS_FIR_BL8848_ID
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BLF_N_TAPS, iFirBLFCoefs}, // FILTER_DEFS_FIR_BLF_ID
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BL19288_N_TAPS, iFirBL19288Coefs}, // FILTER_DEFS_FIR_BL19288_ID
{FIR_TYPE_SYNC, FILTER_DEFS_FIR_BL17696_N_TAPS, iFirBL17696}, // FILTER_DEFS_FIR_BL17696_ID
{FIR_TYPE_OS2, FILTER_DEFS_FIR_UP_N_TAPS, iFirUPCoefs}, // FILTER_DEFS_FIR_UP_ID
{FIR_TYPE_OS2, FILTER_DEFS_FIR_UP4844_N_TAPS, iFirUP4844Coefs}, // FILTER_DEFS_FIR_UP4844_ID
{FIR_TYPE_OS2, FILTER_DEFS_FIR_UPF_N_TAPS, iFirUPFCoefs}, // FILTER_DEFS_FIR_UPF_ID
{FIR_TYPE_OS2, FILTER_DEFS_FIR_UP192176_N_TAPS, iFirUP192176Coefs}, // FILTER_DEFS_FIR_UP192176_ID
{FIR_TYPE_DS2, FILTER_DEFS_FIR_DS_N_TAPS, iFirDSCoefs}, // FILTER_DEFS_FIR_DS_ID
{FIR_TYPE_SYNC, 0, 0} // FILTER_DEFS_FIR_NONE_ID
};
// FIR filters coefficients
int iFirBLCoefs[FILTER_DEFS_FIR_BL_N_TAPS] = {
#include FILTER_DEFS_FIR_BL_FILE
};
int iFirBL9644Coefs[FILTER_DEFS_FIR_BL9644_N_TAPS] = {
#include FILTER_DEFS_FIR_BL9644_FILE
};
int iFirBL8848[FILTER_DEFS_FIR_BL8848_N_TAPS] = {
#include FILTER_DEFS_FIR_BL8848_FILE
};
int iFirBLFCoefs[FILTER_DEFS_FIR_BLF_N_TAPS] = {
#include FILTER_DEFS_FIR_BLF_FILE
};
int iFirBL19288Coefs[FILTER_DEFS_FIR_BL19288_N_TAPS] = {
#include FILTER_DEFS_FIR_BL19288_FILE
};
int iFirBL17696[FILTER_DEFS_FIR_BL17696_N_TAPS] = {
#include FILTER_DEFS_FIR_BL17696_FILE
};
int iFirUPCoefs[FILTER_DEFS_FIR_UP_N_TAPS] = {
#include FILTER_DEFS_FIR_UP_FILE
};
int iFirUP4844Coefs[FILTER_DEFS_FIR_UP4844_N_TAPS] = {
#include FILTER_DEFS_FIR_UP4844_FILE
};
int iFirUPFCoefs[FILTER_DEFS_FIR_UPF_N_TAPS] = {
#include FILTER_DEFS_FIR_UPF_FILE
};
int iFirUP192176Coefs[FILTER_DEFS_FIR_UP192176_N_TAPS] = {
#include FILTER_DEFS_FIR_UP192176_FILE
};
int iFirDSCoefs[FILTER_DEFS_FIR_DS_N_TAPS] = {
#include FILTER_DEFS_FIR_DS_FILE
};
int iFirOSCoefs[FILTER_DEFS_FIR_OS_N_TAPS] = {
#include FILTER_DEFS_FIR_OS_FILE
};
// ADFIR filters descriptor
ADFIRDescriptor_t sADFirDescriptor =
{
FILTER_DEFS_ADFIR_PHASE_N_TAPS, FILTER_DEFS_ADFIR_N_PHASES + 2, (int *)iADFirCoefs
};
// ADFIR filter coefficients
int iADFirPrototypeCoefs[FILTER_DEFS_ADFIR_PROTOTYPE_N_TAPS] = {
#include FILTER_DEFS_ADFIR_PROTOTYPE_FILE
};
#if SRC_USE_VPU
int iADFirCoefs[FILTER_DEFS_ADFIR_PHASE_N_TAPS][FILTER_DEFS_ADFIR_N_PHASES + 2];
#else
int iADFirCoefs[FILTER_DEFS_ADFIR_N_PHASES + 2][FILTER_DEFS_ADFIR_PHASE_N_TAPS];
#endif
// PPFIR filters descriptors (ordered by ID)
PPFIRDescriptor_t sPPFirDescriptor[FILTER_DEFS_N_PPFIR_ID] =
{
{FILTER_DEFS_PPFIR_HS294_N_TAPS, FILTER_DEFS_PPFIR_HS294_N_PHASES, iPPFirHS294Coefs}, // FILTER_DEFS_PPFIR_HS294_ID
{FILTER_DEFS_PPFIR_HS320_N_TAPS, FILTER_DEFS_PPFIR_HS320_N_PHASES, iPPFirHS320Coefs}, // FILTER_DEFS_PPFIR_HS320_ID
{0, 0, 0} // FILTER_DEFS_PPFIR_NONE_ID
};
// PPFIR filters coefficients
int iPPFirHS294Coefs[FILTER_DEFS_PPFIR_HS294_N_TAPS] = {
#include FILTER_DEFS_PPFIR_HS294_FILE
};
int iPPFirHS320Coefs[FILTER_DEFS_PPFIR_HS320_N_TAPS] = {
#include FILTER_DEFS_PPFIR_HS320_FILE
};
// ===========================================================================
//
// Local Functions prototypes
//
// ===========================================================================
// ===========================================================================
//
// Functions implementations
//
// ===========================================================================

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// Copyright 2016-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
// ===========================================================================
// ===========================================================================
//
// Filters Definitions definition file for the SRC
//
// ===========================================================================
// ===========================================================================
#ifndef _SRC_MRHF_FILTER_DEFS_H_
#define _SRC_MRHF_FILTER_DEFS_H_
#include "use_vpu.h"
// ===========================================================================
//
// Defines
//
// ===========================================================================
// General defines
// ---------------
// SSRC FIR filters IDs
#define FILTER_DEFS_SSRC_FIR_BL_ID 0 // ID of BL FIR filter
#define FILTER_DEFS_SSRC_FIR_BL9644_ID 1 // ID of BL9644 FIR filter
#define FILTER_DEFS_SSRC_FIR_BL8848_ID 2 // ID of BL8848 FIR filter
#define FITLER_DEFS_SSRC_FIR_BL19288_ID 3 // ID of BL19288 FIR filter
#define FILTER_DEFS_SSRC_FIR_BL17696_ID 4 // ID of BL17696 FIR filter
#define FILTER_DEFS_SSRC_FIR_UP_ID 5 // ID of UP FIR filter
#define FILTER_DEFS_SSRC_FIR_UP4844_ID 6 // ID of UP4844 FIR filter
#define FILTER_DEFS_SSRC_FIR_UPF_ID 7 // ID of UPF FIR filter
#define FILTER_DEFS_SSRC_FIR_UP192176_ID 8 // ID of UP192176 FIR filter
#define FILTER_DEFS_SSRC_FIR_DS_ID 9 // ID of DS FIR filter
#define FILTER_DEFS_SSRC_FIR_OS_ID 10 // ID of OS FIR filter
#define FILTER_DEFS_SSRC_FIR_NONE_ID 11 // ID of disabled FIR filter
// ASRC FIR filters IDs
#define FILTER_DEFS_ASRC_FIR_BL_ID 0 // ID of BL FIR filter
#define FILTER_DEFS_ASRC_FIR_BL9644_ID 1 // ID of BL9644 FIR filter
#define FILTER_DEFS_ASRC_FIR_BL8848_ID 2 // ID of BL8848 FIR filter
#define FITLER_DEFS_ASRC_FIR_BLF_ID 3 // ID of BLF FIR filter
#define FITLER_DEFS_ASRC_FIR_BL19288_ID 4 // ID of BL19288 FIR filter
#define FILTER_DEFS_ASRC_FIR_BL17696_ID 5 // ID of BL17696 FIR filter
#define FILTER_DEFS_ASRC_FIR_UP_ID 6 // ID of UP FIR filter
#define FILTER_DEFS_ASRC_FIR_UP4844_ID 7 // ID of UP4844 FIR filter
#define FILTER_DEFS_ASRC_FIR_UPF_ID 8 // ID of UPF FIR filter
#define FILTER_DEFS_ASRC_FIR_UP192176_ID 9 // ID of UP192176 FIR filter
#define FILTER_DEFS_ASRC_FIR_DS_ID 10 // ID of DS FIR filter
#define FILTER_DEFS_ASRC_FIR_NONE_ID 11 // ID of disabled FIR filter
#define FILTER_DEFS_SSRC_N_FIR_ID (FILTER_DEFS_SSRC_FIR_NONE_ID + 1) // Number of FIR IDs corresponding to real FIRs
#define FILTER_DEFS_ASRC_N_FIR_ID (FILTER_DEFS_ASRC_FIR_NONE_ID + 1) // Number of FIR IDs corresponding to real FIRs
// FIR filter number of taps
#define FILTER_DEFS_FIR_BL_N_TAPS 144 // Number of taps of BL FIR filter
#define FILTER_DEFS_FIR_BL9644_N_TAPS 160 // Number of taps of BL9644 FIR filter
#define FILTER_DEFS_FIR_BL8848_N_TAPS 144 // Number of taps of BL8848 filter
#define FILTER_DEFS_FIR_BLF_N_TAPS 96 // Number of taps of BLF FIR filter
#define FILTER_DEFS_FIR_BL19288_N_TAPS 96 // Number of taps of BL19288 filter
#define FILTER_DEFS_FIR_BL17696_N_TAPS 96 // Number of taps of BL17696 filter
#define FILTER_DEFS_FIR_UP_N_TAPS 144 // Number of taps of UP filter
#define FILTER_DEFS_FIR_UP4844_N_TAPS 160 // Number of taps of UP4844 filter
#define FILTER_DEFS_FIR_UPF_N_TAPS 96 // Number of taps of UPF filter
#define FILTER_DEFS_FIR_UP192176_N_TAPS 96 // Number of taps of UP192176 filter
#define FILTER_DEFS_FIR_DS_N_TAPS 32 // Number of taps of DS filter
#define FILTER_DEFS_FIR_OS_N_TAPS 32 // Number of taps of OS filter
#define FILTER_DEFS_FIR_MAX_TAPS_LONG FILTER_DEFS_FIR_BL9644_N_TAPS // Maximum number of taps for long FIR filter
#define FILTER_DEFS_FIR_MAX_TAPS_SHORT FILTER_DEFS_FIR_DS_N_TAPS // Maximum number of taps for short FIR filter
// FIR filter coefficients files
#if SRC_USE_VPU
#define FILTER_DEFS_FIR_BL_FILE "FilterData/BL.dat" // Coefficients file for BL FIR filter
#define FILTER_DEFS_FIR_BL9644_FILE "FilterData/BL9644.dat" // Coefficients file for BL9644 FIR filter
#define FILTER_DEFS_FIR_BL8848_FILE "FilterData/BL8848.dat" // Coefficients file for BL8848 filter
#define FILTER_DEFS_FIR_BLF_FILE "FilterData/BLF.dat" // Coefficients file for BLF FIR filter
#define FILTER_DEFS_FIR_BL19288_FILE "FilterData/BL19288.dat" // Coefficients file for BL19288 FIR filter
#define FILTER_DEFS_FIR_BL17696_FILE "FilterData/BL17696.dat" // Coefficients file for BL17696 filter
#define FILTER_DEFS_FIR_UP_FILE "FilterData/UP_xs3.dat" // Coefficients file for UP filter
#define FILTER_DEFS_FIR_UP4844_FILE "FilterData/UP4844_xs3.dat" // Coefficients file for UP4844 filter
#define FILTER_DEFS_FIR_UPF_FILE "FilterData/UPF_xs3.dat" // Coefficients file for UPF filter
#define FILTER_DEFS_FIR_UP192176_FILE "FilterData/UP192176_xs3.dat" // Coefficients file for UP192176 filter
#define FILTER_DEFS_FIR_OS_FILE "FilterData/OS_xs3.dat" // Coefficients file for OS filter
#else
#define FILTER_DEFS_FIR_BL_FILE "FilterData/BL.dat" // Coefficients file for BL FIR filter
#define FILTER_DEFS_FIR_BL9644_FILE "FilterData/BL9644.dat" // Coefficients file for BL9644 FIR filter
#define FILTER_DEFS_FIR_BL8848_FILE "FilterData/BL8848.dat" // Coefficients file for BL8848 filter
#define FILTER_DEFS_FIR_BLF_FILE "FilterData/BLF.dat" // Coefficients file for BLF FIR filter
#define FILTER_DEFS_FIR_BL19288_FILE "FilterData/BL19288.dat" // Coefficients file for BL19288 FIR filter
#define FILTER_DEFS_FIR_BL17696_FILE "FilterData/BL17696.dat" // Coefficients file for BL17696 filter
#define FILTER_DEFS_FIR_UP_FILE "FilterData/UP.dat" // Coefficients file for UP filter
#define FILTER_DEFS_FIR_UP4844_FILE "FilterData/UP4844.dat" // Coefficients file for UP4844 filter
#define FILTER_DEFS_FIR_UPF_FILE "FilterData/UPF.dat" // Coefficients file for UPF filter
#define FILTER_DEFS_FIR_UP192176_FILE "FilterData/UP192176.dat" // Coefficients file for UP192176 filter
#define FILTER_DEFS_FIR_OS_FILE "FilterData/OS.dat" // Coefficients file for OS filter
#endif
#define FILTER_DEFS_FIR_DS_FILE "FilterData/DS.dat" // Coefficients file for DS filter
// ADFIR filter number of taps and phases
#define FILTER_DEFS_ADFIR_PROTOTYPE_N_TAPS 1920 // Number of taps of ADFIR filter prototype
#define FILTER_DEFS_ADFIR_N_PHASES 128 // Number of phases of ADFIR filter
#define FILTER_DEFS_ADFIR_PHASE_N_TAPS ((FILTER_DEFS_ADFIR_PROTOTYPE_N_TAPS / FILTER_DEFS_ADFIR_N_PHASES) + 1) // Number of taps per phase
#define FILTER_DEFS_ADFIR_N_TAPS (FILTER_DEFS_ADFIR_N_PHASES + 2) * FILTER_DEFS_ADFIR_PHASE_N_TAPS // Here 130 phases of 16 taps = 2080 coefs
// ADFIR filter coefficients files
#define FILTER_DEFS_ADFIR_PROTOTYPE_FILE "FilterData/ADFir.dat" // Coefficients file for the ADFIR filter (prototype)
// PPFIR filters IDs
#define FILTER_DEFS_PPFIR_HS294_ID 0 // ID of HS294 PPFIR filter
#define FILTER_DEFS_PPFIR_HS320_ID 1 // ID of HS320 PPFIR filter
#define FILTER_DEFS_PPFIR_NONE_ID 2 // ID of disabled PPFIR filter
#define FILTER_DEFS_N_PPFIR_ID (FILTER_DEFS_PPFIR_NONE_ID + 1) // Number of PPFIR IDs corresponding to real PPFIRs
// PPFIR filter number of taps and phases
#define FILTER_DEFS_PPFIR_HS294_N_TAPS 2352 // Number of taps of HS294 PPFIR filter
#define FILTER_DEFS_PPFIR_HS294_N_PHASES 147 // Number of phases of HS294 PPFIR filter
#define FILTER_DEFS_PPFIR_HS320_N_TAPS 2560 // Number of taps of HS320 PPFIR filter
#define FILTER_DEFS_PPFIR_HS320_N_PHASES 160 // Number of phases of HS284 PPFIR filter
#define FILTER_DEFS_PPFIR_PHASE_MAX_TAPS (FILTER_DEFS_PPFIR_HS320_N_TAPS / FILTER_DEFS_PPFIR_HS320_N_PHASES) // Maximum number of taps per phase
#define FILTER_DEFS_PPFIR_PHASE_STEP_0 0
#define FILTER_DEFS_PPFIR_PHASE_STEP_147 147
#define FILTER_DEFS_PPFIR_PHASE_STEP_294 294
#define FILTER_DEFS_PPFIR_PHASE_STEP_160 160
#define FILTER_DEFS_PPFIR_PHASE_STEP_320 320
// PPFIR filter coefficients files
#define FILTER_DEFS_PPFIR_HS294_FILE "FilterData/HS294.dat" // Coefficients file for HS294 PPFIR filter
#define FILTER_DEFS_PPFIR_HS320_FILE "FilterData/HS320.dat" // Coefficients file for HS320 PPFIR filter
// ===========================================================================
//
// Variables
//
// ===========================================================================
// FIR filters descriptors (ordered by ID)
extern FIRDescriptor_t sSSRCFirDescriptor[FILTER_DEFS_SSRC_N_FIR_ID];
extern FIRDescriptor_t sASRCFirDescriptor[FILTER_DEFS_ASRC_N_FIR_ID];
// FIR filters coefficients
extern int iFirBLCoefs[FILTER_DEFS_FIR_BL_N_TAPS];
extern int iFirBL9644Coefs[FILTER_DEFS_FIR_BL9644_N_TAPS];
extern int iFirBL8848[FILTER_DEFS_FIR_BL8848_N_TAPS];
extern int iFirBLFCoefs[FILTER_DEFS_FIR_BLF_N_TAPS];
extern int iFirBL19288Coefs[FILTER_DEFS_FIR_BL19288_N_TAPS];
extern int iFirBL17696[FILTER_DEFS_FIR_BL17696_N_TAPS];
extern int iFirUPCoefs[FILTER_DEFS_FIR_UP_N_TAPS];
extern int iFirUP4844Coefs[FILTER_DEFS_FIR_UP4844_N_TAPS];
extern int iFirUPFCoefs[FILTER_DEFS_FIR_UPF_N_TAPS];
extern int iFirUP192176Coefs[FILTER_DEFS_FIR_UP192176_N_TAPS];
extern int iFirDSCoefs[FILTER_DEFS_FIR_DS_N_TAPS];
extern int iFirOSCoefs[FILTER_DEFS_FIR_OS_N_TAPS];
// ADFIR filter descriptor
extern ADFIRDescriptor_t sADFirDescriptor;
// ADFIR filters coefficients
extern int iADFirPrototypeCoefs[FILTER_DEFS_ADFIR_PROTOTYPE_N_TAPS];
#if SRC_USE_VPU
extern int iADFirCoefs[FILTER_DEFS_ADFIR_PHASE_N_TAPS][FILTER_DEFS_ADFIR_N_PHASES + 2];
#else
extern int iADFirCoefs[FILTER_DEFS_ADFIR_N_PHASES + 2][FILTER_DEFS_ADFIR_PHASE_N_TAPS];
#endif
// PPFIR filters descriptors (ordered by ID)
extern PPFIRDescriptor_t sPPFirDescriptor[FILTER_DEFS_N_PPFIR_ID];
// FIR filters coefficients
extern int iPPFirHS294Coefs[FILTER_DEFS_PPFIR_HS294_N_TAPS];
extern int iPPFirHS320Coefs[FILTER_DEFS_PPFIR_HS320_N_TAPS];
// ===========================================================================
//
// TypeDefs
//
// ===========================================================================
#endif // _SRC_MRHF_FILTER_DEFS_H_

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