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Steven Dan
2025-12-11 09:43:42 +08:00
commit d8b2974133
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11
lib_adat/examples/app_adat_tx_direct_example/CMakeLists.txt Normal file
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cmake_minimum_required(VERSION 3.21)
include($ENV{XMOS_CMAKE_PATH}/xcommon.cmake)
project(app_adat_tx_direct_example)
set(APP_HW_TARGET xk-audio-316-mc.xn)
include(${CMAKE_CURRENT_LIST_DIR}/../deps.cmake)
set(APP_COMPILER_FLAGS -g -DADAT_TX_USE_SHARED_BUFF)
set(XMOS_SANDBOX_DIR ${CMAKE_CURRENT_LIST_DIR}/../../..)
XMOS_REGISTER_APP()

134
lib_adat/examples/app_adat_tx_direct_example/src/main.xc Normal file
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// Copyright 2011-2024 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#include <platform.h>
#include <xs1.h>
#include "adat_tx.h"
extern "C" {
#include "sw_pll.h"
}
/* Port declarations */
buffered out port:32 p_adat_tx = PORT_ADAT_OUT;
in port p_mclk_in = PORT_MCLK_IN;
out port p_ctrl = PORT_CTRL;
on tile[1]: clock clk_audio = XS1_CLKBLK_2;
//:
#define MCLK_FREQUENCY_48 24576000
void board_setup(void)
{
set_port_drive_high(p_ctrl);
// Drive control port to turn on 3V3.
// Bits set to low will be high-z, pulled down.
p_ctrl <: 0xA0;
// Wait for power supplies to be up and stable.
delay_milliseconds(10);
sw_pll_fixed_clock(MCLK_FREQUENCY_48);
while (1) {}
}
#define SINE_TABLE_SIZE 100
const int sine_table[SINE_TABLE_SIZE] =
{
0x0100da00,0x0200b000,0x02fe8100,0x03f94b00,0x04f01100,
0x05e1da00,0x06cdb200,0x07b2aa00,0x088fdb00,0x09646600,
0x0a2f7400,0x0af03700,0x0ba5ed00,0x0c4fde00,0x0ced5f00,
0x0d7dd100,0x0e00a100,0x0e754b00,0x0edb5a00,0x0f326700,
0x0f7a1800,0x0fb22700,0x0fda5b00,0x0ff28a00,0x0ffa9c00,
0x0ff28a00,0x0fda5b00,0x0fb22700,0x0f7a1800,0x0f326700,
0x0edb5a00,0x0e754b00,0x0e00a100,0x0d7dd100,0x0ced5f00,
0x0c4fde00,0x0ba5ed00,0x0af03700,0x0a2f7400,0x09646600,
0x088fdb00,0x07b2aa00,0x06cdb200,0x05e1da00,0x04f01100,
0x03f94b00,0x02fe8100,0x0200b000,0x0100da00,0x00000000,
0xfeff2600,0xfdff5000,0xfd017f00,0xfc06b500,0xfb0fef00,
0xfa1e2600,0xf9324e00,0xf84d5600,0xf7702500,0xf69b9a00,
0xf5d08c00,0xf50fc900,0xf45a1300,0xf3b02200,0xf312a100,
0xf2822f00,0xf1ff5f00,0xf18ab500,0xf124a600,0xf0cd9900,
0xf085e800,0xf04dd900,0xf025a500,0xf00d7600,0xf0056400,
0xf00d7600,0xf025a500,0xf04dd900,0xf085e800,0xf0cd9900,
0xf124a600,0xf18ab500,0xf1ff5f00,0xf2822f00,0xf312a100,
0xf3b02200,0xf45a1300,0xf50fc900,0xf5d08c00,0xf69b9a00,
0xf7702500,0xf84d5600,0xf9324e00,0xfa1e2600,0xfb0fef00,
0xfc06b500,0xfd017f00,0xfdff5000,0xfeff2600,0x00000000,
};
unsigned samples[8];
/* Data generation task */
void generate_samples(chanend c) {
int count1 = 0;
int count2 = 0;
int count4 = 0;
outuint(c, MCLK_FREQUENCY_48 / 48000); // clock multiplier value
outuint(c, 1); // S/MUX value
unsafe {
volatile unsigned * unsafe sample_ptr = (unsigned * unsafe) &samples[0];
outuint(c, (unsigned) sample_ptr);
}
while(1) {
inuint(c);
// Update sample values
samples[0] = sine_table[count1]; // 500Hz sine
samples[1] = sine_table[SINE_TABLE_SIZE - 1 - count1]; // 500Hz sine, phase-shifted from channel 0
samples[2] = sine_table[count2]; // 1000Hz sine
samples[3] = sine_table[SINE_TABLE_SIZE - 1 - count2]; // 1000Hz sine, phase-shifted from channel 2
samples[4] = sine_table[count4]; // 2000Hz sine
samples[5] = sine_table[SINE_TABLE_SIZE - 1 - count4]; // 2000Hz sine, phase-shifted from channel 4
samples[6] = sine_table[count1]; // same as channel 0
samples[7] = sine_table[SINE_TABLE_SIZE - 1 - count1]; // same as channel 1
unsafe {
volatile unsigned * unsafe sample_ptr = (unsigned * unsafe) &samples[0];
outuint(c, (unsigned) sample_ptr);
}
// Handle rollover of the sine_table array indices
count1 += 1;
count2 += 2;
count4 += 4;
if (count1 == SINE_TABLE_SIZE) {
count1 = 0;
count2 = 0;
count4 = 0;
} else if (count2 == SINE_TABLE_SIZE) {
count2 = 0;
count4 = 0;
} else if (count4 == SINE_TABLE_SIZE) {
count4 = 0;
}
}
}
//:
void transmit_adat(chanend c)
{
/* Setup ports and clocks */
set_clock_src(clk_audio, p_mclk_in);
configure_out_port_no_ready(p_adat_tx, clk_audio, 0);
set_clock_fall_delay(clk_audio, 7);
start_clock(clk_audio);
adat_tx_port(c, p_adat_tx);
}
/* Top-level main */
int main(void)
{
chan c;
par
{
on tile[0]: board_setup();
on tile[1]: transmit_adat(c);
on tile[1]: generate_samples(c);
}
return 0;
}
//:

93
lib_adat/examples/app_adat_tx_direct_example/src/xk-audio-316-mc.xn Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Network xmlns="http://www.xmos.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.xmos.com http://www.xmos.com">
<Type>Board</Type>
<Name>xcore.ai MC Audio Board</Name>
<Declarations>
<Declaration>tileref tile[2]</Declaration>
</Declarations>
<Packages>
<Package id="0" Type="XS3-UnA-1024-TQ128">
<Nodes>
<Node Id="0" InPackageId="0" Type="XS3-L16A-1024" Oscillator="24MHz" SystemFrequency="600MHz" ReferenceFrequency="100MHz">
<Boot>
<Source Location="bootFlash"/>
</Boot>
<Tile Number="0" Reference="tile[0]">
<Port Location="XS1_PORT_1B" Name="PORT_SQI_CS"/>
<Port Location="XS1_PORT_1C" Name="PORT_SQI_SCLK"/>
<Port Location="XS1_PORT_4B" Name="PORT_SQI_SIO"/>
<!-- Various ctrl signals -->
<Port Location="XS1_PORT_8D" Name="PORT_CTRL"/>
<!-- I2C -->
<Port Location="XS1_PORT_1L" Name="PORT_I2C_SCL"/>
<Port Location="XS1_PORT_1M" Name="PORT_I2C_SDA"/>
<!-- Clocking -->
<Port Location="XS1_PORT_16B" Name="PORT_MCLK_COUNT"/>
<Port Location="XS1_PORT_1D" Name="PORT_MCLK_IN_USB"/>
<Port Location="XS1_PORT_1A" Name="PORT_PLL_REF"/>
<!-- Audio Ports: Digital -->
<Port Location="XS1_PORT_1O" Name="PORT_ADAT_IN"/> <!-- N: Coax O: Optical -->
<Port Location="XS1_PORT_1N" Name="PORT_SPDIF_IN"/> <!-- N: Coax O: Optical -->
</Tile>
<Tile Number="1" Reference="tile[1]">
<!-- Audio Ports: I2S -->
<Port Location="XS1_PORT_1D" Name="PORT_MCLK_IN"/>
<Port Location="XS1_PORT_16B" Name="PORT_MCLK_COUNT_2"/>
<Port Location="XS1_PORT_1B" Name="PORT_I2S_LRCLK"/>
<Port Location="XS1_PORT_1C" Name="PORT_I2S_BCLK"/>
<Port Location="XS1_PORT_1P" Name="PORT_I2S_DAC0"/>
<port Location="XS1_PORT_1O" Name="PORT_I2S_DAC1"/>
<port Location="XS1_PORT_1N" Name="PORT_I2S_DAC2"/>
<port Location="XS1_PORT_1M" Name="PORT_I2S_DAC3"/>
<Port Location="XS1_PORT_1I" Name="PORT_I2S_ADC0"/>
<Port Location="XS1_PORT_1J" Name="PORT_I2S_ADC1"/>
<Port Location="XS1_PORT_1K" Name="PORT_I2S_ADC2"/>
<Port Location="XS1_PORT_1L" Name="PORT_I2S_ADC3"/>
<!-- Audio Ports: Digital -->
<Port Location="XS1_PORT_1G" Name="PORT_ADAT_OUT"/> <!-- A: Coax G: Optical -->
<Port Location="XS1_PORT_1A" Name="PORT_SPDIF_OUT"/> <!-- A: Coax G: Optical -->
<!-- MIDI -->
<Port Location="XS1_PORT_1F" Name="PORT_MIDI_IN"/>
<Port Location="XS1_PORT_4C" Name="PORT_MIDI_OUT"/> <!-- bit[0] -->
</Tile>
</Node>
</Nodes>
</Package>
</Packages>
<Nodes>
<Node Id="2" Type="device:" RoutingId="0x8000">
<Service Id="0" Proto="xscope_host_data(chanend c);">
<Chanend Identifier="c" end="3"/>
</Service>
</Node>
</Nodes>
<Links>
<Link Encoding="2wire" Delays="5clk" Flags="XSCOPE">
<LinkEndpoint NodeId="0" Link="XL0"/>
<LinkEndpoint NodeId="2" Chanend="1"/>
</Link>
</Links>
<ExternalDevices>
<Device NodeId="0" Tile="0" Class="SQIFlash" Name="bootFlash" PageSize="256" SectorSize="4096" NumPages="16384">
<Attribute Name="PORT_SQI_CS" Value="PORT_SQI_CS"/>
<Attribute Name="PORT_SQI_SCLK" Value="PORT_SQI_SCLK"/>
<Attribute Name="PORT_SQI_SIO" Value="PORT_SQI_SIO"/>
</Device>
</ExternalDevices>
<JTAGChain>
<JTAGDevice NodeId="0"/>
</JTAGChain>
</Network>