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Steven Dan
2025-12-11 09:43:42 +08:00
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33
lib_spdif/examples/app_spdif_tx_example/Makefile Normal file
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# The TARGET variable determines what target system the application is
# compiled for. It either refers to an XN file in the source directories
# or a valid argument for the --target option when compiling.
TARGET = xk-audio-316-mc.xn
# The APP_NAME variable determines the name of the final .xe file. It should
# not include the .xe postfix. If left blank the name will default to
# the project name
APP_NAME =
# The flags passed to xcc when building the application
# You can also set the following to override flags for a particular language:
#
# XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS
#
# If the variable XCC_MAP_FLAGS is set it overrides the flags passed to
# xcc for the final link (mapping) stage.
XCC_FLAGS = -O2 -g
# The USED_MODULES variable lists other module used by the application.
USED_MODULES = lib_spdif lib_xassert
#=============================================================================
# The following part of the Makefile includes the common build infrastructure
# for compiling XMOS applications. You should not need to edit below here.
XMOS_MAKE_PATH ?= ../..
include $(XMOS_MAKE_PATH)/xcommon/module_xcommon/build/Makefile.common

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lib_spdif/examples/app_spdif_tx_example/README.rst Normal file
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app_example_tx
==============
:scope: General Use
:description: app_example_tx

129
lib_spdif/examples/app_spdif_tx_example/src/main.xc Normal file
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// Copyright 2014-2023 XMOS LIMITED.
// This Software is subject to the terms of the XMOS Public Licence: Version 1.
#include <xs1.h>
#include <platform.h>
#include <spdif.h>
#include <xassert.h>
on tile[0]: out port p_ctrl = XS1_PORT_8D;
on tile[0]: in port p_i2c_sda = XS1_PORT_1M;
on tile[0]: in port p_coax_rx = XS1_PORT_1N;
on tile[0]: in port p_opt_rx = XS1_PORT_1O;
on tile[0]: in port p_word_clk = XS1_PORT_1P;
on tile[1]: out buffered port:32 p_spdif_tx = XS1_PORT_1A;
on tile[1]: in port p_mclk_in = XS1_PORT_1D;
on tile[1]: clock clk_audio = XS1_CLKBLK_1;
// Found solution: IN 24.000MHz, OUT 24.576000MHz, VCO 2457.60MHz, RD 1, FD 102.400 (m = 2, n = 5), OD 5, FOD 5, ERR 0.0ppm
// Measure: 100Hz-40kHz: ~8ps
// 100Hz-1MHz: 63ps.
// 100Hz high pass: 127ps.
#define APP_PLL_CTL_24M 0x0A006500
#define APP_PLL_DIV_24M 0x80000004
#define APP_PLL_FRAC_24M 0x80000104
#define SAMPLE_FREQUENCY_HZ 96000
#define MCLK_FREQUENCY_48 24576000
#define SINE_TABLE_SIZE 100
const int32_t sine_table[SINE_TABLE_SIZE] =
{
0x0100da00,0x0200b000,0x02fe8100,0x03f94b00,0x04f01100,
0x05e1da00,0x06cdb200,0x07b2aa00,0x088fdb00,0x09646600,
0x0a2f7400,0x0af03700,0x0ba5ed00,0x0c4fde00,0x0ced5f00,
0x0d7dd100,0x0e00a100,0x0e754b00,0x0edb5a00,0x0f326700,
0x0f7a1800,0x0fb22700,0x0fda5b00,0x0ff28a00,0x0ffa9c00,
0x0ff28a00,0x0fda5b00,0x0fb22700,0x0f7a1800,0x0f326700,
0x0edb5a00,0x0e754b00,0x0e00a100,0x0d7dd100,0x0ced5f00,
0x0c4fde00,0x0ba5ed00,0x0af03700,0x0a2f7400,0x09646600,
0x088fdb00,0x07b2aa00,0x06cdb200,0x05e1da00,0x04f01100,
0x03f94b00,0x02fe8100,0x0200b000,0x0100da00,0x00000000,
0xfeff2600,0xfdff5000,0xfd017f00,0xfc06b500,0xfb0fef00,
0xfa1e2600,0xf9324e00,0xf84d5600,0xf7702500,0xf69b9a00,
0xf5d08c00,0xf50fc900,0xf45a1300,0xf3b02200,0xf312a100,
0xf2822f00,0xf1ff5f00,0xf18ab500,0xf124a600,0xf0cd9900,
0xf085e800,0xf04dd900,0xf025a500,0xf00d7600,0xf0056400,
0xf00d7600,0xf025a500,0xf04dd900,0xf085e800,0xf0cd9900,
0xf124a600,0xf18ab500,0xf1ff5f00,0xf2822f00,0xf312a100,
0xf3b02200,0xf45a1300,0xf50fc900,0xf5d08c00,0xf69b9a00,
0xf7702500,0xf84d5600,0xf9324e00,0xfa1e2600,0xfb0fef00,
0xfc06b500,0xfd017f00,0xfdff5000,0xfeff2600,0x00000000,
};
void generate_samples(chanend c) {
int i = 0;
spdif_tx_reconfigure_sample_rate(c,
SAMPLE_FREQUENCY_HZ,
MCLK_FREQUENCY_48);
while(1) {
// Generate a sine wave
int sample = sine_table[i];
i = (i + 1) % SINE_TABLE_SIZE;
spdif_tx_output(c, sample, sample);
}
}
// Set secondary (App) PLL control register
void set_app_pll_init (tileref tile, int app_pll_ctl)
{
// delay_microseconds(500);
// Disable the PLL
write_node_config_reg(tile, XS1_SSWITCH_SS_APP_PLL_CTL_NUM, (app_pll_ctl & 0xF7FFFFFF));
// Enable the PLL to invoke a reset on the appPLL.
write_node_config_reg(tile, XS1_SSWITCH_SS_APP_PLL_CTL_NUM, app_pll_ctl);
// Must write the CTL register twice so that the F and R divider values are captured using a running clock.
write_node_config_reg(tile, XS1_SSWITCH_SS_APP_PLL_CTL_NUM, app_pll_ctl);
// Now disable and re-enable the PLL so we get the full 5us reset time with the correct F and R values.
write_node_config_reg(tile, XS1_SSWITCH_SS_APP_PLL_CTL_NUM, (app_pll_ctl & 0xF7FFFFFF));
write_node_config_reg(tile, XS1_SSWITCH_SS_APP_PLL_CTL_NUM, app_pll_ctl);
// Wait for PLL to lock.
delay_microseconds(500);
}
void app_pll_setup(void)
{
set_app_pll_init(tile[0], APP_PLL_CTL_24M);
write_node_config_reg(tile[0], XS1_SSWITCH_SS_APP_PLL_FRAC_N_DIVIDER_NUM, APP_PLL_FRAC_24M);
write_node_config_reg(tile[0], XS1_SSWITCH_SS_APP_CLK_DIVIDER_NUM, APP_PLL_DIV_24M);
}
void board_setup(void)
{
//////// BOARD SETUP ////////
// Define other tile 0 ports as inputs to avoid driving them when writing to 8 bit port.
p_i2c_sda :> void;
p_coax_rx :> void;
p_opt_rx :> void;
p_word_clk :> void;
// Drive control port to turn on 3V3 and set MCLK_DIR/EXT_PLL_SEL to select App PLL.
p_ctrl <: 0xA0;
// Wait for power supplies to be up and stable.
delay_milliseconds(10);
/////////////////////////////
}
int main(void) {
chan c_spdif;
par
{
on tile[0]: {
board_setup();
app_pll_setup();
while(1) {};
}
on tile[1]: {
spdif_tx_port_config(p_spdif_tx, clk_audio, p_mclk_in, 7);
start_clock(clk_audio);
spdif_tx(p_spdif_tx, c_spdif);
}
on tile[1]: generate_samples(c_spdif);
}
return 0;
}

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lib_spdif/examples/app_spdif_tx_example/src/xk-audio-316-mc.xn Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<Network xmlns="http://www.xmos.com"
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
xsi:schemaLocation="http://www.xmos.com http://www.xmos.com">
<Type>Board</Type>
<Name>xcore.ai MC Audio Board</Name>
<Declarations>
<Declaration>tileref tile[2]</Declaration>
</Declarations>
<Packages>
<Package id="0" Type="XS3-UnA-1024-FB265">
<Nodes>
<Node Id="0" InPackageId="0" Type="XS3-L16A-1024" Oscillator="24MHz" SystemFrequency="600MHz" ReferenceFrequency="100MHz">
<Boot>
<Source Location="bootFlash"/>
</Boot>
<Tile Number="0" Reference="tile[0]">
<Port Location="XS1_PORT_1B" Name="PORT_SQI_CS"/>
<Port Location="XS1_PORT_1C" Name="PORT_SQI_SCLK"/>
<Port Location="XS1_PORT_4B" Name="PORT_SQI_SIO"/>
<!-- Various ctrl signals -->
<Port Location="XS1_PORT_8D" Name="PORT_CTRL"/>
<!-- I2C -->
<Port Location="XS1_PORT_1L" Name="PORT_I2C_SCL"/>
<Port Location="XS1_PORT_1M" Name="PORT_I2C_SDA"/>
<!-- Clocking -->
<Port Location="XS1_PORT_16B" Name="PORT_MCLK_COUNT"/>
<Port Location="XS1_PORT_1D" Name="PORT_MCLK_IN_USB"/>
<Port Location="XS1_PORT_1A" Name="PORT_PLL_REF"/>
<!-- Audio Ports: Digital -->
<Port Location="XS1_PORT_1O" Name="PORT_ADAT_IN"/> <!-- N: Coax O: Optical -->
<Port Location="XS1_PORT_1N" Name="PORT_SPDIF_IN"/> <!-- N: Coax O: Optical -->
</Tile>
<Tile Number="1" Reference="tile[1]">
<!-- Audio Ports: I2S -->
<Port Location="XS1_PORT_1D" Name="PORT_MCLK_IN"/>
<Port Location="XS1_PORT_1B" Name="PORT_I2S_LRCLK"/>
<Port Location="XS1_PORT_1C" Name="PORT_I2S_BCLK"/>
<Port Location="XS1_PORT_1P" Name="PORT_I2S_DAC0"/>
<port Location="XS1_PORT_1O" Name="PORT_I2S_DAC1"/>
<port Location="XS1_PORT_1N" Name="PORT_I2S_DAC2"/>
<port Location="XS1_PORT_1M" Name="PORT_I2S_DAC3"/>
<Port Location="XS1_PORT_1I" Name="PORT_I2S_ADC0"/>
<Port Location="XS1_PORT_1J" Name="PORT_I2S_ADC1"/>
<Port Location="XS1_PORT_1K" Name="PORT_I2S_ADC2"/>
<Port Location="XS1_PORT_1L" Name="PORT_I2S_ADC3"/>
<!-- Audio Ports: Digital -->
<Port Location="XS1_PORT_1G" Name="PORT_ADAT_OUT"/> <!-- A: Coax G: Optical -->
<Port Location="XS1_PORT_1A" Name="PORT_SPDIF_OUT"/> <!-- A: Coax G: Optical -->
<!-- MIDI -->
<Port Location="XS1_PORT_1F" Name="PORT_MIDI_IN"/>
<Port Location="XS1_PORT_4C" Name="PORT_MIDI_OUT"/> <!-- bit[0] -->
</Tile>
</Node>
</Nodes>
</Package>
</Packages>
<Nodes>
<Node Id="2" Type="device:" RoutingId="0x8000">
<Service Id="0" Proto="xscope_host_data(chanend c);">
<Chanend Identifier="c" end="3"/>
</Service>
</Node>
</Nodes>
<Links>
<Link Encoding="2wire" Delays="5clk" Flags="XSCOPE">
<LinkEndpoint NodeId="0" Link="XL0"/>
<LinkEndpoint NodeId="2" Chanend="1"/>
</Link>
</Links>
<ExternalDevices>
<Device NodeId="0" Tile="0" Class="SQIFlash" Name="bootFlash" PageSize="256" SectorSize="4096" NumPages="8192">
<Attribute Name="PORT_SQI_CS" Value="PORT_SQI_CS"/>
<Attribute Name="PORT_SQI_SCLK" Value="PORT_SQI_SCLK"/>
<Attribute Name="PORT_SQI_SIO" Value="PORT_SQI_SIO"/>
</Device>
</ExternalDevices>
<JTAGChain>
<JTAGDevice NodeId="0"/>
</JTAGChain>
</Network>