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lib_sw_pll/examples/shared/src/clock_gen.c

@@ -0,0 +1,60 @@
+// Copyright 2023 XMOS LIMITED.
+// This Software is subject to the terms of the XMOS Public Licence: Version 1.
+
+#include <xs1.h>
+#include <stdio.h>
+#include <xcore/hwtimer.h>
+#include <xcore/port.h>
+
+#include "sw_pll_common.h"
+
+#define DO_CLOCKS \
+printf("Ref Hz: %d\n", clock_rate >> 1); \
+\
+unsigned cycle_ticks_int = XS1_TIMER_HZ / clock_rate; \
+unsigned cycle_ticks_remaidner = XS1_TIMER_HZ % clock_rate; \
+unsigned carry = 0; \
+\
+period_trig += XS1_TIMER_HZ * 1; \
+unsigned time_now = hwtimer_get_time(period_tmr); \
+while(TIMER_TIMEAFTER(period_trig, time_now)) \
+{ \
+    port_out(p_clock_gen, port_val); \
+    hwtimer_wait_until(clock_tmr, time_trig); \
+    time_trig += cycle_ticks_int; \
+    carry += cycle_ticks_remaidner; \
+    if(carry >= clock_rate){ \
+        time_trig++; \
+        carry -= clock_rate; \
+    } \
+    port_val ^= 1; \
+    time_now = hwtimer_get_time(period_tmr); \
+}
+
+void clock_gen(unsigned ref_frequency, unsigned ppm_range) // Step from - to + this
+{
+    unsigned clock_rate = ref_frequency * 2; // Note double because we generate edges at this rate
+
+    unsigned clock_rate_low = (unsigned)(clock_rate * (1.0 - (float)ppm_range / 1000000.0));
+    unsigned clock_rate_high = (unsigned)(clock_rate * (1.0 + (float)ppm_range / 1000000.0));
+    unsigned step_size = (clock_rate_high - clock_rate_low) / 20;
+
+    printf("Sweep range: %d %d %d, step size: %d\n", clock_rate_low / 2, clock_rate / 2, clock_rate_high / 2, step_size);
+
+    hwtimer_t period_tmr = hwtimer_alloc();
+    unsigned period_trig = hwtimer_get_time(period_tmr);
+
+    hwtimer_t clock_tmr = hwtimer_alloc();
+    unsigned time_trig = hwtimer_get_time(clock_tmr);
+
+    port_t p_clock_gen = PORT_I2S_BCLK;
+    port_enable(p_clock_gen);
+    unsigned port_val = 1;
+
+    for(unsigned clock_rate = clock_rate_low; clock_rate <= clock_rate_high; clock_rate += 2 * step_size){
+        DO_CLOCKS
+    }
+    for(unsigned clock_rate = clock_rate_high; clock_rate > clock_rate_low; clock_rate -= 2 * step_size){
+        DO_CLOCKS
+    }
+}

lib_sw_pll/examples/shared/src/clock_gen.h

@@ -0,0 +1,9 @@
+// Copyright 2023 XMOS LIMITED.
+// This Software is subject to the terms of the XMOS Public Licence: Version 1.
+
+// Runs a task in a thread that produces a clock that sweeps a reference clock
+// between + and - the ppm value specified. 
+//
+// param ref_frequency  Nominal frequency in Hz
+// param ppm_range      The range to sweep
+void clock_gen(unsigned ref_frequency, unsigned ppm_range);

lib_sw_pll/examples/shared/src/resource_setup.c

@@ -0,0 +1,43 @@
+// Copyright 2023 XMOS LIMITED.
+// This Software is subject to the terms of the XMOS Public Licence: Version 1.
+
+#include <stdio.h>
+#include "resource_setup.h"
+
+void setup_ref_and_mclk_ports_and_clocks(port_t p_mclk, xclock_t clk_mclk, port_t p_clock_counter, xclock_t clk_ref_clk, port_t p_ref_clk_timing)
+{
+    // Create clock from mclk port and use it to clock the p_clock_counter port.
+    clock_enable(clk_mclk);
+    port_enable(p_mclk);
+    clock_set_source_port(clk_mclk, p_mclk);
+
+    // Clock p_clock_counter from MCLK
+    port_enable(p_clock_counter);
+    port_set_clock(p_clock_counter, clk_mclk);
+
+    clock_start(clk_mclk);
+
+    // Create clock from ref_clock_port and use it to clock the p_clock_counter port.
+    clock_enable(clk_ref_clk);
+    clock_set_source_port(clk_ref_clk, p_clock_counter);
+    port_enable(p_ref_clk_timing);
+    port_set_clock(p_ref_clk_timing, clk_ref_clk);
+
+    clock_start(clk_ref_clk);
+}
+
+
+void setup_recovered_ref_clock_output(port_t p_recovered_ref_clk, xclock_t clk_recovered_ref_clk, port_t p_mclk, unsigned divider)
+{
+    // Connect clock block with divide to mclk
+    clock_enable(clk_recovered_ref_clk);
+    clock_set_source_port(clk_recovered_ref_clk, p_mclk);
+    clock_set_divide(clk_recovered_ref_clk, divider / 2);
+    printf("Divider: %u\n", divider);
+
+    // Output the divided mclk on a port
+    port_enable(p_recovered_ref_clk);
+    port_set_clock(p_recovered_ref_clk, clk_recovered_ref_clk);
+    port_set_out_clock(p_recovered_ref_clk);
+    clock_start(clk_recovered_ref_clk);
+}

lib_sw_pll/examples/shared/src/resource_setup.h

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+// Copyright 2023 XMOS LIMITED.
+// This Software is subject to the terms of the XMOS Public Licence: Version 1.
+
+#include <xcore/port.h>
+
+#pragma once
+
+// Sets up the provided resources so that we can count PLL output clocks.
+// We do this by clocking the input reference clock port with the output from the PLL
+// and its internal counter is used to count the PLL clock cycles(normal timers cannot count custom clocks)
+// It also sets up a dummy port clocked by the input reference to act as a timing barrier so that 
+// the output clock count can be precisely sampled. 
+//
+// param p_mclk             The mclk output port (Always P1D on tile[1])
+// param clk_mclk           The clockblock for mclk out 
+// param p_clock_counter    The port used for counting mclks - in this case the ref input clock
+// param clk_ref_clk        The clockblock for the timing barrier
+// param p_ref_clk_timing   The port used for t he timing barrier
+void setup_ref_and_mclk_ports_and_clocks(port_t p_mclk, xclock_t clk_mclk, port_t p_clock_counter, xclock_t clk_ref_clk, port_t p_ref_clk_timing);
+
+// Sets up a divided version of the PLL output so it can visually be compared (eg. on a DSO)
+// with the input reference clock to the PLL
+//
+// param p_recovered_ref_clk    The port used to drive the recovered and divided clock
+// param clk_recovered_ref_clk  The clockblock used to drive the recovered and divided clock 
+// param p_mclk                 The mclk output port (Always P1D on tile[1])
+// param divider                The divide value from mclk to the divided output
+void setup_recovered_ref_clock_output(port_t p_recovered_ref_clk, xclock_t clk_recovered_ref_clk, port_t p_mclk, unsigned divider);