@@ -41,6 +41,7 @@ unsigned g_uac_mode = 1; // 2 for UAC2.0, 1 for UAC1.0
unsigned g_uac_mode = 2; // 2 for UAC2.0, 1 for UAC1.0
#endif
unsafe client interface i2c_master_if i_i2c_client;
audio_sampling g_new_playback_format, g_playback_format;
audio_type g_new_audio_type, g_audio_type = 0;
unsigned g_mute_enable = 0;
@@ -106,179 +107,11 @@ void board_setup()
debug_printf("board_setup OK.");
}
#if 0
//Tile 0
unsafe client interface i2c_master_if i_i2c_client_t0;
static uint8_t mic_vol = 0x2b;
#define MIN_MIC_VOL_LEVEL 0
#define MAX_MIC_VOL_LEVEL 0x37
//static inline int CODEC_REGWRITE(uint8_t reg, uint8_t val);
i2c_regop_res_t i2c_reg_write_t0(uint8_t device_addr, uint8_t reg, uint8_t data)
{
uint8_t a_data[2] = {reg, data};
size_t n;
unsafe
{
i_i2c_client_t0.write(device_addr, a_data, 2, n, 1);
}
if (n == 0)
{
return I2C_REGOP_DEVICE_NACK;
}
if (n < 2)
{
return I2C_REGOP_INCOMPLETE;
}
return I2C_REGOP_SUCCESS;
}
static inline int CODEC_REGWRITE_t0(uint8_t reg, uint8_t val)
{
i2c_regop_res_t ret;
ret = i2c_reg_write_t0(AIC3204_I2C_DEVICE_ADDR, reg, val);
//ret = rtos_i2c_master_reg_write(i2c_master_ctx, AIC3204_I2C_DEVICE_ADDR, reg, val);
if (ret == I2C_REGOP_SUCCESS) {
return 0;
} else {
return -1;
}
}
int i2c_codec_mic_vol_up(void)
{
//delay_milliseconds(20);
if (mic_vol < MAX_MIC_VOL_LEVEL) {
mic_vol++;
if ( (CODEC_REGWRITE_t0(AIC3204_PAGE_CTRL, 1) == 0) && (CODEC_REGWRITE_t0(AIC3204_OP_PWR_CTRL, 0x00) == 0) ) {
return 0;
} else {
return -1;
}
}
return 0;
}
//------------------------------------------------------------------------------------
/* Working around not being able to extend an unsafe interface (Bugzilla #18670)*/
i2c_regop_res_t i2c_reg_write(uint8_t device_addr, uint8_t reg, uint8_t data)
{
uint8_t a_data[2] = {reg, data};
size_t n;
unsafe
{
i_i2c_client.write(device_addr, a_data, 2, n, 1);
}
if (n == 0)
{
return I2C_REGOP_DEVICE_NACK;
}
if (n < 2)
{
return I2C_REGOP_INCOMPLETE;
}
return I2C_REGOP_SUCCESS;
}
uint8_t i2c_reg_read(uint8_t device_addr, uint8_t reg, i2c_regop_res_t &result)
{
uint8_t a_reg[1] = {reg};
uint8_t data[1] = {0};
size_t n;
i2c_res_t res;
unsafe
{
res = i_i2c_client.write(device_addr, a_reg, 1, n, 0);
if (n != 1)
{
result = I2C_REGOP_DEVICE_NACK;
i_i2c_client.send_stop_bit();
return 0;
}
res = i_i2c_client.read(device_addr, data, 1, 1);
}
if (res == I2C_ACK)
{
result = I2C_REGOP_SUCCESS;
}
else
{
result = I2C_REGOP_DEVICE_NACK;
}
return data[0];
}
unsafe client interface i2c_master_if i_i2c_client;
#if 0
uint8_t CODEC_REGREAD(int regAddr)
{
i2c_regop_res_t result ;
return i2c_reg_read(AIC3204_I2C_DEVICE_ADDR, regAddr, &result);
}
#endif
void CODEC_REGWRITE(int regAddr, int regData)
{
i2c_regop_res_t result = i2c_reg_write(AIC3204_I2C_DEVICE_ADDR, regAddr, regData);
// asert(result == I2C_REGOP_SUCCESS && msg("I2C write reg failed"));
}
/*
* Writes a value to a register in the AIC3204 DAC chip.
*/
static inline int CODEC_REGWRITE(uint8_t reg, uint8_t val)
{
i2c_regop_res_t ret;
ret = i2c_reg_write(AIC3204_I2C_DEVICE_ADDR, reg, val);
//ret = rtos_i2c_master_reg_write(i2c_master_ctx, AIC3204_I2C_DEVICE_ADDR, reg, val);
if (ret == I2C_REGOP_SUCCESS) {
return 0;
} else {
return -1;
}
}
#endif
unsafe chanend uc_audiohw;
typedef enum {
AUDIOHW_CMD_REGWR,
AUDIOHW_CMD_REGRD
} audioHwCmd_t;
static inline void CODEC_REGWRITE(unsigned reg, unsigned val)
{
unsafe {
uc_audiohw <: (unsigned) AUDIOHW_CMD_REGWR;
uc_audiohw <: reg;
uc_audiohw <: val;
}
}
static inline void CODEC_REGREAD(unsigned reg, unsigned val)
{
unsafe {
uc_audiohw <: (unsigned) AUDIOHW_CMD_REGRD;
uc_audiohw <: reg;
uc_audiohw :> val;
}
}
static inline void CODEC_IC_REGREAD(unsigned reg, unsigned &val, client interface i2c_master_if i2c)
// 改动原因： ， （ ） ，
// 这会引入未定义行为/潜在栈破坏， （ ）
// 这里改为返回i2c_regop_res_t并正确回填val，
i2c_regop_res_t CODEC_IC_REGREAD(unsigned reg, unsigned &val)
{
i2c_regop_res_t result;
@@ -289,18 +122,19 @@ static inline void CODEC_IC_REGREAD(unsigned reg, unsigned &val, client interfac
unsafe
{
res = i2c .write(CODEC_I2C_DEVICE_ADDR, a_reg, 1, n, 0);
res = i_i2c_client .write(CODEC_I2C_DEVICE_ADDR, a_reg, 1, n, 0);
if (n != 1)
{
result = I2C_REGOP_DEVICE_NACK;
i2c .send_stop_bit();
return 0 ;
result = I2C_REGOP_DEVICE_NACK; // 改动原因： （
i_i2c_client .send_stop_bit();
return result ;
}
res = i2c .read(CODEC_I2C_DEVICE_ADDR, data, 1, 1);
res = i_i2c_client .read(CODEC_I2C_DEVICE_ADDR, data, 1, 1);
}
data[0] = val;
// 改动原因：修复方向错误，应将读到的 data[0]写回到 val。
val = data[0];
debug_printf("CODEC_IC_REGREAD reg: %d, val: %d\n", reg, data[0]);
if (res == I2C_ACK)
@@ -311,33 +145,38 @@ static inline void CODEC_IC_REGREAD(unsigned reg, unsigned &val, client interfac
{
result = I2C_REGOP_DEVICE_NACK;
}
// return data[0];
return result;
}
static inline void CODEC_IC_REGWRITE(unsigned reg, unsigned val, client interface i2c_master_if i2c)
// 改动原因： ，
// 这里将返回类型改为i2c_regop_res_t，
i2c_regop_res_t CODEC_IC_REGWRITE(unsigned reg, unsigned val)
{
uint8_t a_data[2] = {reg, val};
size_t n;
unsafe
{
i2c.write( CODEC_I2 C_DEVICE_ADDR, a_data, 2, n, 1 );
debug_printf(" CODEC_IC_REGWRITE reg: %d, val: %d\n", reg, val );
i_i2c_client.write(CODEC_I2C_DEVICE_ADDR, a_data, 2, n, 1);
}
if (n == 0)
{
debug_printf("CODEC_IC_REGWRITE n: %d\n", n);
return I2C_REGOP_DEVICE_NACK;
}
if (n < 2)
{
debug_printf("CODEC_IC_REGWRITE n: %d\n", n);
return I2C_REGOP_INCOMPLETE;
}
debug_printf("CODEC_IC_REGWRITE reg: %d, val: %d\n", reg, val);
debug_printf("CODEC_IC_REGWRITE === reg: %d, val: %d\n", reg, val);
return I2C_REGOP_SUCCESS;
}
// tile 1
static uint8_t mic_vol = 4 0; //84; // default +42dB as 20250408 //56; //0x2b;
uint8_t mic_vol = 6 0; //84; // default +42dB as 20250408 //56; //0x2b;
#define MIN_MIC_VOL_LEVEL 0
#define MAX_MIC_VOL_LEVEL 84 // max +42dB as 20250408 //0x37
#define MIC_VOL_STEP 4
@@ -351,8 +190,8 @@ int i2c_codec_mic_vol_up(void)
if (mic_vol > MAX_MIC_VOL_LEVEL) {
mic_vol = MAX_MIC_VOL_LEVEL;
}
CODEC_REGWRITE(AIC3204_PAGE_CTRL, 1);
CODEC_REGWRITE(0x3c, mic_vol);
CODEC_IC_ REGWRITE(AIC3204_PAGE_CTRL, 1);
CODEC_IC_ REGWRITE(0x3c, mic_vol);
}
debug_printf("vol %d\n", mic_vol);
delay_milliseconds(10);
@@ -369,8 +208,8 @@ int i2c_codec_mic_vol_down(void)
// } else {
mic_vol=mic_vol-MIC_VOL_STEP;
// }
CODEC_REGWRITE(AIC3204_PAGE_CTRL, 1);
CODEC_REGWRITE(0x3c, mic_vol);
CODEC_IC_ REGWRITE(AIC3204_PAGE_CTRL, 1);
CODEC_IC_ REGWRITE(0x3c, mic_vol);
}
debug_printf("vol %d\n", mic_vol);
delay_milliseconds(10);
@@ -381,142 +220,140 @@ int i2c_codec_mic_vol_down(void)
extern void button_task(chanend c_hidSendData, chanend cc_mic_level, chanend c_uac_vol);
void codec_init(void)
{
unsigned page_ctrl;
{
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0x00);
// Initiate SW reset (PLL is powered off as part of reset)
CODEC_IC_REGWRITE(AIC3204_SW_RST, 0x01);
delay_milliseconds(10);
// Program clock settings
// Default is CODEC_CLKIN is from MCLK pin. Don't need to change this.
// Power up NDAC and set to 1
CODEC_IC_REGWRITE(AIC3204_NDAC, 0x81);
CODEC_IC_REGREAD(AIC3204_NDAC, page_ctrl);
debug_printf("page_ctrl: %d\n", page_ctrl);
// Power up MDAC and set to 4
CODEC_IC_REGWRITE(AIC3204_MDAC, 0x84);
// Power up NADC and set to 1
CODEC_IC_REGWRITE(AIC3204_NADC, 0x81);
// Power up MADC and set to 4
CODEC_IC_REGWRITE(AIC3204_MADC, 0x84);
// Program DOSR = 128
CODEC_IC_REGWRITE(AIC3204_DOSR_LSB, 0x80);
// Program AOSR = 128
CODEC_IC_REGWRITE(AIC3204_AOSR, 0x80);
// Set Audio Interface Config: I2S, 24 bits, slave mode, DOUT always driving.
CODEC_IC_REGWRITE(AIC3204_CODEC_IF, 0x20);
// Program the DAC processing block to be used - PRB_P1
CODEC_IC_REGWRITE(AIC3204_DAC_SIG_PROC, 0x01);
// Program the ADC processing block to be used - PRB_R1
CODEC_IC_REGWRITE(AIC3204_ADC_SIG_PROC, 0x01); // 3D-------------------------
// Select Page 1
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0x01);
// Enable the internal AVDD_LDO:
CODEC_IC_REGWRITE(AIC3204_LDO_CTRL, 0x09);
//
// Program Analog Blocks
// ---------------------
//
// Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO
CODEC_IC_REGWRITE(AIC3204_PWR_CFG, 0x08);
// Enable Master Analog Power Control
CODEC_IC_REGWRITE(AIC3204_LDO_CTRL, 0x01);
// Set Common Mode voltages: Full Chip CM to 0.9V and Output Common Mode for Headphone to 1.65V and HP powered from LDOin @ 3.3V.
CODEC_IC_REGWRITE(AIC3204_CM_CTRL, 0x33);
// Set PowerTune Modes
// Set the Left & Right DAC PowerTune mode to PTM_P3/4. Use Class-AB driver.
CODEC_IC_REGWRITE(AIC3204_PLAY_CFG1, 0x00);
CODEC_IC_REGWRITE(AIC3204_PLAY_CFG2, 0x00);
// Set ADC PowerTune mode PTM_R4.
CODEC_IC_REGWRITE(AIC3204_ADC_PTM, 0x00);
// Set MicPGA startup delay to 3.1ms
CODEC_IC_REGWRITE(AIC3204_AN_IN_CHRG, 0x31);
// Set the REF charging time to 40ms
CODEC_IC_REGWRITE(AIC3204_REF_STARTUP, 0x01);
// HP soft stepping settings for optimal pop performance at power up
// Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling
// capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
CODEC_IC_REGWRITE(AIC3204_HP_START, 0x25);
// Route Left DAC to HPL
CODEC_IC_REGWRITE(AIC3204_HPL_ROUTE, 0x08);
// Route Right DAC to HPR
CODEC_IC_REGWRITE(AIC3204_HPR_ROUTE, 0x08);
CODEC_IC_REGWRITE(0x0e, 0x08);
CODEC_IC_REGWRITE(0x0f, 0x08);
CODEC_IC_REGWRITE(0x12, 0x3a);
CODEC_IC_REGWRITE(0x13, 0x3a); // Gain-0DB
// We are using Line input with low gain for PGA so can use 40k input R but lets stick to 20k for now.
// Route IN2_L to LEFT_P with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_LPGA_P_ROUTE, 0x20); //---
// Route IN2_R to LEFT_M with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_LPGA_N_ROUTE, 0x20); //---
// Route IN1_R to RIGHT_P with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_RPGA_P_ROUTE, 0x80); //---
// Route IN1_L to RIGHT_M with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_RPGA_N_ROUTE, 0x20); //---
// Unmute HPL and set gain to 0dB
CODEC_IC_REGWRITE(AIC3204_HPL_GAIN, 0x06);
// Unmute HPR and set gain to 0dB
CODEC_IC_REGWRITE(AIC3204_HPR_GAIN, 0x06);
// Unmute Left MICPGA, Set Gain to 0dB.
CODEC_IC_REGWRITE(AIC3204_LPGA_VOL, 0x00);
// Unmute Right MICPGA, Set Gain to 0dB.
CODEC_IC_REGWRITE(AIC3204_RPGA_VOL, 0x00);
// Power up HPL and HPR drivers
CODEC_IC_REGWRITE(AIC3204_OP_PWR_CTRL, 0x30); // HP powerUp
// CODEC_REGWRITE(AIC3204_OP_PWR_CTRL, 0x0C); // LO powerUP
// Wait for 2.5 sec for soft stepping to take effect
// vTaskDelay(pdMS_TO_TICKS(2500));
delay_milliseconds(20);
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0x00);
// Power up the Left and Right DAC Channels. Route Left data to Left DAC and Right data to Right DAC.
// DAC Vol control soft step 1 step per DAC word clock.
CODEC_IC_REGWRITE(AIC3204_DAC_CH_SET1, 0xd4);
// Power up Left and Right ADC Channels, ADC vol ctrl soft step 1 step per ADC word clock.
CODEC_IC_REGWRITE(AIC3204_ADC_CH_SET, 0xc0);
// Unmute Left and Right DAC digital volume control
CODEC_IC_REGWRITE(AIC3204_DAC_CH_SET2, 0x00);
// Unmute Left and Right ADC Digital Volume Control.
CODEC_IC_REGWRITE(AIC3204_ADC_FGA_MUTE, 0x00);
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 1); // page1
CODEC_IC_REGWRITE(0x47, 0x32); // analog input quick charging configure
CODEC_IC_REGWRITE(0x7b, 0x01); // power up config
CODEC_IC_REGWRITE(0x33, 0x60); //---------0x78 used fail-------jian added ----MICBIAS
CODEC_IC_REGWRITE(0x37, 0x80);
CODEC_IC_REGWRITE(0x39, 0x20); // IN1L to RIGHT MICPGA with 20k ohm
CODEC_IC_REGWRITE(0x3c, mic_vol /*40*/); // Right MICPGA VOL --5a-45DB 5e--47db :3d--ap实际测试25DB增益---跟客户样品一致 （ ）
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0); // page0
CODEC_IC_REGWRITE(0x51, 0xc0); //
CODEC_IC_REGWRITE(0x52, 0x00); //
//CODEC_IC_REGWRITE(AIC3204_ADC_CH1_SET, 0x0C); // ADC L_CH vol
//CODEC_IC_REGWRITE(AIC3204_ADC_CH2_SET, 0x0C); // ADC R_CH vol
}
}
void AudioHwRemote(chanend c_hidSendData, chanend cc_mic_level, chanend c_uac_vol)
{
i2c_master_if i2c[1];
unsigned page_ctrl;
board_setup();
delay_milliseconds(200);
par {
i2c_master(i2c, 1, p_scl, p_sda, 1 00);
{
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0x00, i2c[0]) ;
// Initiate SW reset (PLL is powered off as part of reset)
CODEC_IC_REGWRITE(AIC3204_SW_RST, 0x01, i2c[0]);
delay_milliseconds(10);
// Program clock settings
// Default is CODEC_CLKIN is from MCLK pin. Don't need to change this.
// Power up NDAC and set to 1
CODEC_IC_REGWRITE(AIC3204_NDAC, 0x81, i2c[0]);
CODEC_IC_REGREAD(AIC3204_NDAC, page_ctrl, i2c[0]);
debug_printf("page_ctrl: %d\n", page_ctrl);
// Power up MDAC and set to 4
CODEC_IC_REGWRITE(AIC3204_MDAC, 0x84, i2c[0]);
// Power up NADC and set to 1
CODEC_IC_REGWRITE(AIC3204_NADC, 0x81, i2c[0]);
// Power up MADC and set to 4
CODEC_IC_REGWRITE(AIC3204_MADC, 0x84, i2c[0]);
// Program DOSR = 128
CODEC_IC_REGWRITE(AIC3204_DOSR_LSB, 0x80, i2c[0]);
// Program AOSR = 128
CODEC_IC_REGWRITE(AIC3204_AOSR, 0x80, i2c[0]);
// Set Audio Interface Config: I2S, 24 bits, slave mode, DOUT always driving.
CODEC_IC_REGWRITE(AIC3204_CODEC_IF, 0x20, i2c[0]);
// Program the DAC processing block to be used - PRB_P1
CODEC_IC_REGWRITE(AIC3204_DAC_SIG_PROC, 0x01, i2c[0]);
// Program the ADC processing block to be used - PRB_R1
CODEC_IC_REGWRITE(AIC3204_ADC_SIG_PROC, 0x01, i2c[0]); // 3D-------------------------
// Select Page 1
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0x01, i2c[0]);
// Enable the internal AVDD_LDO:
CODEC_IC_REGWRITE(AIC3204_LDO_CTRL, 0x09, i2c[0]);
//
// Program Analog Blocks
// ---------------------
//
// Disable Internal Crude AVdd in presence of external AVdd supply or before powering up internal AVdd LDO
CODEC_IC_REGWRITE(AIC3204_PWR_CFG, 0x08, i2c[0]);
// Enable Master Analog Power Control
CODEC_IC_REGWRITE(AIC3204_LDO_CTRL, 0x01, i2c[0]);
// Set Common Mode voltages: Full Chip CM to 0.9V and Output Common Mode for Headphone to 1.65V and HP powered from LDOin @ 3.3V.
CODEC_IC_REGWRITE(AIC3204_CM_CTRL, 0x33, i2c[0]);
// Set PowerTune Modes
// Set the Left & Right DAC PowerTune mode to PTM_P3/4. Use Class-AB driver.
CODEC_IC_REGWRITE(AIC3204_PLAY_CFG1, 0x00, i2c[0]);
CODEC_IC_REGWRITE(AIC3204_PLAY_CFG2, 0x00, i2c[0]);
// Set ADC PowerTune mode PTM_R4.
CODEC_IC_REGWRITE(AIC3204_ADC_PTM, 0x00, i2c[0]);
// Set MicPGA startup delay to 3.1ms
CODEC_IC_REGWRITE(AIC3204_AN_IN_CHRG, 0x31, i2c[0]);
// Set the REF charging time to 40ms
CODEC_IC_REGWRITE(AIC3204_REF_STARTUP, 0x01, i2c[0]);
// HP soft stepping settings for optimal pop performance at power up
// Rpop used is 6k with N = 6 and soft step = 20usec. This should work with 47uF coupling
// capacitor. Can try N=5,6 or 7 time constants as well. Trade-off delay vs “pop” sound.
CODEC_IC_REGWRITE(AIC3204_HP_START, 0x25, i2c[0]);
// Route Left DAC to HPL
CODEC_IC_REGWRITE(AIC3204_HPL_ROUTE, 0x08, i2c[0]);
// Route Right DAC to HPR
CODEC_IC_REGWRITE(AIC3204_HPR_ROUTE, 0x08, i2c[0]);
CODEC_IC_REGWRITE(0x0e, 0x08, i2c[0]);
CODEC_IC_REGWRITE(0x0f, 0x08, i2c[0]);
CODEC_IC_REGWRITE(0x12, 0x3a, i2c[0]);
CODEC_IC_REGWRITE(0x13, 0x3a, i2c[0]); //Gain-0DB
// We are using Line input with low gain for PGA so can use 40k input R but lets stick to 20k for now.
// Route IN2_L to LEFT_P with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_LPGA_P_ROUTE, 0x20, i2c[0]); //---
// Route IN2_R to LEFT_M with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_LPGA_N_ROUTE, 0x20, i2c[0]); //---
// Route IN1_R to RIGHT_P with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_RPGA_P_ROUTE, 0x80, i2c[0]); //---
// Route IN1_L to RIGHT_M with 20K input impedance
CODEC_IC_REGWRITE(AIC3204_RPGA_N_ROUTE, 0x20, i2c[0]); //---
// Unmute HPL and set gain to 0dB
CODEC_IC_REGWRITE(AIC3204_HPL_GAIN, 0x06, i2c[0]);
// Unmute HPR and set gain to 0dB
CODEC_IC_REGWRITE(AIC3204_HPR_GAIN, 0x06, i2c[0]);
// Unmute Left MICPGA, Set Gain to 0dB.
CODEC_IC_REGWRITE(AIC3204_LPGA_VOL, 0x00, i2c[0]);
// Unmute Right MICPGA, Set Gain to 0dB.
CODEC_IC_REGWRITE(AIC3204_RPGA_VOL, 0x00, i2c[0]);
// Power up HPL and HPR drivers
CODEC_IC_REGWRITE(AIC3204_OP_PWR_CTRL, 0x30, i2c[0]); // HP powerUp
//CODEC_REGWRITE(AIC3204_OP_PWR_CTRL, 0x0C); // LO powerUP
// Wait for 2.5 sec for soft stepping to take effect
//vTaskDelay(pdMS_TO_TICKS(2500));
delay_milliseconds(20);
CODEC_IC_REGWRITE(AIC3204_PAGE_CTRL, 0x00, i2c[0]);
// Power up the Left and Right DAC Channels. Route Left data to Left DAC and Right data to Right DAC.
// DAC Vol control soft step 1 step per DAC word clock.
CODEC_IC_REGWRITE(AIC3204_DAC_CH_SET1, 0xd4, i2c[0]);
// Power up Left and Right ADC Channels, ADC vol ctrl soft step 1 step per ADC word clock.
CODEC_IC_REGWRITE(AIC3204_ADC_CH_SET, 0xc0, i2c[0]);
// Unmute Left and Right DAC digital volume control
CODEC_IC_REGWRITE(AIC3204_DAC_CH_SET2, 0x00, i2c[0]);
// Unmute Left and Right ADC Digital Volume Control.
CODEC_IC_REGWRITE(AIC3204_ADC_FGA_MUTE, 0x00, i2c[0]);
CODEC_IC_REGWRITE( AIC3204_PAGE_CTRL, 1, i2c[0]); //page1
CODEC_IC_REGWRITE( 0x47, 0x32, i2c[0]); //analog input quick charging configure
CODEC_IC_REGWRITE( 0x7b, 0x01, i2c[0]); //power up config
CODEC_IC_REGWRITE( 0x33, 0x60, i2c[0]); //---------0x78 used fail-------jian added ----MICBIAS
CODEC_IC_REGWRITE( 0x37, 0x80, i2c[0]);
CODEC_IC_REGWRITE( 0x39, 0x20, i2c[0]); // IN1L to RIGHT MICPGA with 20k ohm
CODEC_IC_REGWRITE( 0x3c, mic_vol/*40*/, i2c[0]); // Right MICPGA VOL --5a-45DB 5e--47db :3d--ap实际测试25DB增益---跟客户样品一致 （ ）
CODEC_IC_REGWRITE( AIC3204_PAGE_CTRL, 0, i2c[0]); // page0
CODEC_IC_REGWRITE( 0x51, 0xc0, i2c[0]); //
CODEC_IC_REGWRITE( 0x52, 0x00, i2c[0]); //
i2c[0].shutdown();
i2c_master(i2c, 1, p_scl, p_sda, 3 00);
{
unsafe {i_i2c_client = i2c[0];}
button_task(c_hidSendData, cc_mic_level, c_uac_vol);
}
}
button_task(c_hidSendData, cc_mic_level, c_uac_vol);
}
// 改动原因： ，
void AudioHwRemote2(chanend c, client interface i2c_master_if i2c)
{
// 改动原因： ，
}
}
Steven Dan