28 lines
1.7 KiB
C
28 lines
1.7 KiB
C
// Copyright 2023 XMOS LIMITED.
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// This Software is subject to the terms of the XMOS Public Licence: Version 1.
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#include <xcore/port.h>
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#pragma once
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// Sets up the provided resources so that we can count PLL output clocks.
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// We do this by clocking the input reference clock port with the output from the PLL
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// and its internal counter is used to count the PLL clock cycles(normal timers cannot count custom clocks)
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// It also sets up a dummy port clocked by the input reference to act as a timing barrier so that
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// the output clock count can be precisely sampled.
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//
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// param p_mclk The mclk output port (Always P1D on tile[1])
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// param clk_mclk The clockblock for mclk out
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// param p_clock_counter The port used for counting mclks - in this case the ref input clock
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// param clk_ref_clk The clockblock for the timing barrier
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// param p_ref_clk_timing The port used for t he timing barrier
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void setup_ref_and_mclk_ports_and_clocks(port_t p_mclk, xclock_t clk_mclk, port_t p_clock_counter, xclock_t clk_ref_clk, port_t p_ref_clk_timing);
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// Sets up a divided version of the PLL output so it can visually be compared (eg. on a DSO)
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// with the input reference clock to the PLL
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//
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// param p_recovered_ref_clk The port used to drive the recovered and divided clock
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// param clk_recovered_ref_clk The clockblock used to drive the recovered and divided clock
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// param p_mclk The mclk output port (Always P1D on tile[1])
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// param divider The divide value from mclk to the divided output
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void setup_recovered_ref_clock_output(port_t p_recovered_ref_clk, xclock_t clk_recovered_ref_clk, port_t p_mclk, unsigned divider); |