63 lines
1.6 KiB
ReStructuredText
63 lines
1.6 KiB
ReStructuredText
lib_sw_pll change log
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=====================
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2.2.0
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-----
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* FIXED: Enable PLL output after delay to allow it to settle
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* FIXED: Fixed frequency settings for 11,289,600Hz
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2.1.0
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-----
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* ADDED: Support for XCommon CMake build system
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* ADDED: Reset PI controller state API
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* ADDED: Fixed frequency (non phase-locked) clock PLL API
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* FIXED: Init resets PI controller state
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* FIXED: Now compiles from XC using XCommon
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* ADDED: Guard source code with __XS3A__ to allow library inclusion in non-
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xcore-ai projects
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* CHANGED: Reduce PLL initialisation stabilisation delay from 10 ms to 500 us
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* ADDED: Split SDM init function to allow separation across tiles
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* FIXED: Use non-ACK write to PLL in Sigma Delta Modulator
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2.0.0
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* ADDED: Double integral term to controller
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* ADDED: Sigma Delta Modulator option for PLL
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* CHANGED: Refactored Python model into analogous objects
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1.1.0
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-----
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* ADDED: Function to reset the constants and PI controller state at runtime
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* CHANGED: Framework repositories used by the examples
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1.0.0
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-----
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* ADDED: Low-level error input API
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* FIXED: Divide by zero exception when not using ref clk compensation
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0.3.0
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-----
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* ADDED: Documentation
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* ADDED: Simulator can now generate a modulated test tone to measure jitter
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* CHANGED: Updated tools version to 15.2.1
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0.2.0
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* REMOVED: support for Kii term (speed optimisation)
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* CHANGED: used pre-calculated divide to improve cycle usage
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* CHANGED: use of const in API
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* FIXED: possible overflow where mclk_inc * refclk_inc is > 32b
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0.1.0
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-----
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* ADDED: initial version
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