93 lines
3.8 KiB
ReStructuredText
93 lines
3.8 KiB
ReStructuredText
lib_sw_pll
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==========
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:Version: 2.2.0
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:Vendor: XMOS
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This library contains software that, together with the on-chip application PLL, provides a PLL that will generate a clock that is phase-locked to an input clock.
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It supports both Look Up Table (LUT) and Sigma Delta Modulated (SDM) Digitally Controlled Oscillators (DCO), a Phase Frequency Detector (PFD) and
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configurable Proportional Integral (PI) controllers which together form a hybrid Software/Hardware Phase Locked Loop (PLL).
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Examples are provided showing a master clock locking to a low frequency input reference clock and also to an I2S slave interface.
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In addition, an API providing a range of fixed clocks supporting common master clock frequencies between 11.2896 MHz and 49.152 MHz is available
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in cases where phase locking is not required.
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*********************************
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Building and running the examples
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*********************************
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Ensure a correctly configured installation of the XMOS tools and open an XTC command shell. Please check that the XMOS tools are correctly
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sourced by running the following command::
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$ xcc
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xcc: no input files
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.. note::
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Instructions for installing and configuring the XMOS tools appear on `the XMOS web site <https://www.xmos.ai/software-tools/>`_.
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Clone the lib_sw_pll repository::
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git clone git@github.com:xmos/lib_sw_pll.git
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cd lib_sw_pll
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Place the fwk_core and fwk_io repositories in the modules directory of lib_sw_pll. These are required dependencies for the example apps.
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To do so, from the root of lib_sw_pll (where this read me file exists) type::
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mkdir modules
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cd modules
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git clone --recurse-submodules git@github.com:xmos/fwk_core.git
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git clone --recurse-submodules git@github.com:xmos/fwk_io.git
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cd ..
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.. note::
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The fwk_core and fwk_io repositories have not been sub-moduled into this Git repository because only the examples depend upon them.
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Run the following commands in the lib_sw_pll root folder to build the firmware.
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On linux::
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cmake -B build -DCMAKE_TOOLCHAIN_FILE=modules/fwk_io/xmos_cmake_toolchain/xs3a.cmake
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cd build
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make simple_lut simple_sdm i2s_slave_lut
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On Windows::
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cmake -G "Ninja" -B build -DCMAKE_TOOLCHAIN_FILE=modules/fwk_io/xmos_cmake_toolchain/xs3a.cmake
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cd build
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ninja simple_lut simple_sdm i2s_slave_lut
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To run the firmware, first connect LRCLK and BCLK (connects the test clock output to the PLL reference input)
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and run the following command where <my_example> can be *simple_lut* or *simple_sdm* which use the XCORE-AI-EXPLORER board
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or *i2s_slave_lut* which uses the XK-VOICE-SQ66 board::
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xrun --xscope <my_example>.xe
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For simple_xxx.xe, to see the PLL lock, put one scope probe on either LRCLK/BCLK (reference input) and the other on PORT_I2S_DAC_DATA to see the
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recovered clock which has been hardware divided back down to the same rate as the input reference clock.
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For i2s_slave_lut.xe you will need to connect a 48kHz I2S master to the LRCLK, BCLK pins. You may then observe the I2S input data being
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looped back to the output and the MCLK being generated. A divided version of MCLK is output on PORT_I2S_DATA2 which allows
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direct comparison of the input reference (LRCLK) with the recovered clock at the same, and locked, frequency.
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*********************************
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Generating new PLL configurations
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*********************************
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Please see `doc/rst/sw_pll.rst` for further details on how to design and build new sw_pll configurations. This covers the tradeoff between lock range,
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oscillator noise and resource usage.
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Required Software (dependencies)
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================================
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* None
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Documentation
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=============
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You can find the documentation for this software in the /doc directory of the package.
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Support
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=======
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This package is supported by XMOS Ltd. Issues can be raised against the software at: http://www.xmos.com/support
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