400 lines
15 KiB
Python
400 lines
15 KiB
Python
# Copyright 2023 XMOS LIMITED.
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# This Software is subject to the terms of the XMOS Public Licence: Version 1.
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from sw_pll.app_pll_model import register_file, app_pll_frac_calc
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import matplotlib.pyplot as plt
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import numpy as np
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import os
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import re
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from pathlib import Path
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"""
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This file contains implementations of digitally controlled oscillators.
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It uses the app_pll_model underneath to turn a control signal into a
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calculated output frequency.
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It currently contains two implementations of DCO:
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- A lookup table version which is efficient in computation and offers
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a range of frequencies based on a pre-calculated look up table (LUT)
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- A Sigma Delta Modulator which typically uses a dedicated thread to
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run the modulator but results in lower noise in the audio spectrum
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"""
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lock_status_lookup = {-1 : "UNLOCKED LOW", 0 : "LOCKED", 1 : "UNLOCKED HIGH"}
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lock_count_threshold = 10
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##############################
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# LOOK UP TABLE IMPLEMENTATION
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##############################
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class lut_dco:
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"""
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This class parses a pre-generated fractions.h file and builds a lookup table so that the values can be
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used by the sw_pll simulation. It may be used directly but is generally used a sub class of error_to_pll_output_frequency.
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"""
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def __init__(self, header_file = "fractions.h", verbose=False): # fixed header_file name by pll_calc.py
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"""
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Constructor for the LUT DCO. Reads the pre-calculated header filed and produces the LUT which contains
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the pll fractional register settings (16b) for each of the entries. Also a
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"""
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self.lut, self.min_frac, self.max_frac = self._read_lut_header(header_file)
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input_freq, F, R, f, p, OD, ACD = self._parse_register_file(register_file)
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self.app_pll = app_pll_frac_calc(input_freq, F, R, f, p, OD, ACD)
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self.last_output_frequency = self.app_pll.update_frac_reg(self.lut[self.get_lut_size() // 2] | app_pll_frac_calc.frac_enable_mask)
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self.lock_status = -1
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self.lock_count = lock_count_threshold
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def _read_lut_header(self, header_file):
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"""
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read and parse the pre-written LUT
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"""
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if not os.path.exists(header_file):
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assert False, f"Please initialize a lut_dco to produce a parsable header file {header_file}"
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with open(header_file) as hdr:
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header = hdr.readlines()
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min_frac = 1.0
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max_frac = 0.0
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for line in header:
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regex_ne = fr"frac_values_?\d*\[(\d+)].*"
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match = re.search(regex_ne, line)
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if match:
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num_entries = int(match.groups()[0])
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# print(f"num_entries: {num_entries}")
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lut = np.zeros(num_entries, dtype=np.uint16)
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regex_fr = r"0x([0-9A-F]+).+Index:\s+(\d+).+=\s(0.\d+)"
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match = re.search(regex_fr, line)
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if match:
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reg, idx, frac = match.groups()
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reg = int(reg, 16)
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idx = int(idx)
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frac = float(frac)
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min_frac = frac if frac < min_frac else min_frac
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max_frac = frac if frac > max_frac else max_frac
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lut[idx] = reg
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# print(f"min_frac: {min_frac} max_frac: {max_frac}")
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return lut, min_frac, max_frac
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def _parse_register_file(self, register_file):
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"""
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This method reads the pre-saved register setup comments from get_pll_solution and parses them into parameters that
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can be used for later simulation.
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"""
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if not os.path.exists(register_file):
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assert False, f"Please initialize a lut_dco to produce a parsable register setup file {register_file}"
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with open(register_file) as rf:
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reg_file = rf.read().replace('\n', '')
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input_freq = int(re.search(r".+Input freq:\s+(\d+).+", reg_file).groups()[0])
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F = int(re.search(r".+F:\s+(\d+).+", reg_file).groups()[0])
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R = int(re.search(r".+R:\s+(\d+).+", reg_file).groups()[0])
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f = int(re.search(r".+f:\s+(\d+).+", reg_file).groups()[0])
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p = int(re.search(r".+p:\s+(\d+).+", reg_file).groups()[0])
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OD = int(re.search(r".+OD:\s+(\d+).+", reg_file).groups()[0])
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ACD = int(re.search(r".+ACD:\s+(\d+).+", reg_file).groups()[0])
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return input_freq, F, R, f, p, OD, ACD
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def get_lut(self):
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"""
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Return the look up table
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"""
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return self.lut
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def get_lut_size(self):
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"""
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Return the size of look up table
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"""
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return np.size(self.lut)
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def print_stats(self, target_output_frequency):
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"""
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Returns a summary of the LUT range and steps.
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"""
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lut = self.get_lut()
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steps = np.size(lut)
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register = int(lut[0])
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min_freq = self.app_pll.update_frac_reg(register | app_pll_frac_calc.frac_enable_mask)
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register = int(lut[steps // 2])
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mid_freq = self.app_pll.update_frac_reg(register | app_pll_frac_calc.frac_enable_mask)
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register = int(lut[-1])
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max_freq = self.app_pll.update_frac_reg(register | app_pll_frac_calc.frac_enable_mask)
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ave_step_size = (max_freq - min_freq) / steps
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print(f"LUT min_freq: {min_freq:.0f}Hz")
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print(f"LUT mid_freq: {mid_freq:.0f}Hz")
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print(f"LUT max_freq: {max_freq:.0f}Hz")
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print(f"LUT entries: {steps} ({steps*2} bytes)")
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print(f"LUT average step size: {ave_step_size:.6}Hz, PPM: {1e6 * ave_step_size/mid_freq:.6}")
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print(f"PPM range: {1e6 * (1 - target_output_frequency / min_freq):.6}")
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print(f"PPM range: +{1e6 * (max_freq / target_output_frequency - 1):.6}")
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return min_freq, mid_freq, max_freq, steps
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def plot_freq_range(self):
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"""
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Generates a plot of the frequency range of the LUT and
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visually shows the spacing of the discrete frequencies
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that it can produce.
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"""
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frequencies = []
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for step in range(self.get_lut_size()):
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register = int(self.lut[step])
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self.app_pll.update_frac_reg(register | app_pll_frac_calc.frac_enable_mask)
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frequencies.append(self.app_pll.get_output_frequency())
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plt.clf()
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plt.plot(frequencies, color='green', marker='.', label='frequency')
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plt.title('PLL fractional range', fontsize=14)
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plt.xlabel(f'LUT index', fontsize=14)
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plt.ylabel('Frequency', fontsize=10)
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plt.legend(loc="upper right")
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plt.grid(True)
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# plt.show()
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plt.savefig("lut_dco_range.png", dpi=150)
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def get_frequency_from_dco_control(self, dco_ctrl):
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"""
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given a set_point, a LUT, and an APP_PLL, calculate the frequency
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"""
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if dco_ctrl is None:
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return self.last_output_frequency, self.lock_status
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num_entries = self.get_lut_size()
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set_point = int(dco_ctrl)
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if set_point < 0:
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set_point = 0
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self.lock_status = -1
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self.lock_count = lock_count_threshold
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elif set_point >= num_entries:
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set_point = num_entries - 1
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self.lock_status = 1
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self.lock_count = lock_count_threshold
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else:
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set_point = set_point
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if self.lock_count > 0:
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self.lock_count -= 1
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else:
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self.lock_status = 0
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register = int(self.lut[set_point])
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output_frequency = self.app_pll.update_frac_reg(register | app_pll_frac_calc.frac_enable_mask)
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self.last_output_frequency = output_frequency
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return output_frequency, self.lock_status
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######################################
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# SIGMA DELTA MODULATOR IMPLEMENTATION
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######################################
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class sdm:
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"""
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Experimental - taken from lib_xua synchronous branch
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Third order, 9 level output delta sigma. 20 bit unsigned input.
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"""
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# Limits for SDM modulator for stability
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sdm_in_max = 980000
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sdm_in_min = 60000
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def __init__(self):
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# Delta sigma modulator state
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self.sdm_x1 = 0
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self.sdm_x2 = 0
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self.sdm_x3 = 0
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# # generalized version without fixed point shifts. WIP!!
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# # takes a Q20 number from 60000 to 980000 (or 0.0572 to 0.934)
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# # This is work in progress - the integer model matches the firmware better
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# def do_sigma_delta(self, sdm_in):
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# if sdm_in > self.sdm_in_max:
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# print(f"SDM Pos clip: {sdm_in}, {self.sdm_in_max}")
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# sdm_in = self. sdm_in_max
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# self.lock_status = 1
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# elif sdm_in < self.sdm_in_min:
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# print(f"SDM Neg clip: {sdm_in}, {self.sdm_in_min}")
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# sdm_in = self.sdm_in_min
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# self.lock_status = -1
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# else:
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# self.lock_status = 0
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# sdm_out = int(self.sdm_x3 * 0.002197265625)
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# if sdm_out > 8:
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# sdm_out = 8
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# if sdm_out < 0:
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# sdm_out = 0
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# self.sdm_x3 += int((self.sdm_x2 * 0.03125) - (sdm_out * 768))
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# self.sdm_x2 += int((self.sdm_x1 * 0.03125) - (sdm_out * 16384))
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# self.sdm_x1 += int(sdm_in - (sdm_out * 131072))
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# return int(sdm_out), self.lock_status
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def do_sigma_delta_int(self, sdm_in):
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# takes a Q20 number from 60000 to 980000 (or 0.0572 to 0.934)
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# Third order, 9 level output delta sigma. 20 bit unsigned input.
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sdm_in = int(sdm_in)
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sdm_out = ((self.sdm_x3<<4) + (self.sdm_x3<<1)) >> 13
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if sdm_out > 8:
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sdm_out = 8
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if sdm_out < 0:
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sdm_out = 0
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self.sdm_x3 += (self.sdm_x2>>5) - (sdm_out<<9) - (sdm_out<<8)
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self.sdm_x2 += (self.sdm_x1>>5) - (sdm_out<<14)
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self.sdm_x1 += sdm_in - (sdm_out<<17)
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return sdm_out
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class sigma_delta_dco(sdm):
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"""
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DCO based on the sigma delta modulator
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PLL solution profiles depending on target output clock
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These are designed to work with a SDM either running at
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1MHz:
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- 10ps jitter 100Hz-40kHz with very low freq noise floor -100dBc
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or 500kHz:
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- 50ps jitter 100Hz-40kHz with low freq noise floor -93dBc.
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"""
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profiles = {"24.576_1M": {"input_freq":24000000, "F":int(147.455 - 1), "R":1 - 1, "f":5 - 1, "p":11 - 1, "OD":6 - 1, "ACD":6 - 1, "output_frequency":24.576e6, "mod_init":478151, "sdm_rate":1000000},
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"22.5792_1M": {"input_freq":24000000, "F":int(135.474 - 1), "R":1 - 1, "f":9 - 1, "p":19 - 1, "OD":6 - 1, "ACD":6 - 1, "output_frequency":22.5792e6, "mod_init":498283, "sdm_rate":1000000},
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"24.576_500k": {"input_freq":24000000, "F":int(278.529 - 1), "R":2 - 1, "f":9 - 1, "p":17 - 1, "OD":2 - 1, "ACD":17 - 1, "output_frequency":24.576e6, "mod_init":553648, "sdm_rate":500000},
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"22.5792_500k": {"input_freq":24000000, "F":int(293.529 - 1), "R":2 - 1, "f":9 - 1, "p":17 - 1, "OD":3 - 1, "ACD":13 - 1, "output_frequency":22.5792e6, "mod_init":555326, "sdm_rate":500000}
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}
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def __init__(self, profile):
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"""
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Create a sigmal delta DCO targetting either 24.576 or 22.5792MHz
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"""
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self.profile = profile
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self.p_value = 8 # 8 frac settings + 1 non frac setting
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input_freq, F, R, f, p, OD, ACD, _, _, _ = list(self.profiles[profile].values())
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self.app_pll = app_pll_frac_calc(input_freq, F, R, f, p, OD, ACD)
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self.sdm_out = 0
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self.f = 0
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sdm.__init__(self)
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def _sdm_out_to_freq(self, sdm_out):
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"""
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Translate the SDM steps to register settings
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"""
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if sdm_out == 0:
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# Step 0
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self.f = 0
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return self.app_pll.update_frac(self.f, self.p_value - 1, False)
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else:
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# Steps 1 to 8 inclusive
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self.f = sdm_out - 1
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return self.app_pll.update_frac(self.f, self.p_value - 1, True)
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def do_modulate(self, input):
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"""
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Input a control value and output a SDM signal
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"""
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# self.sdm_out, lock_status = sdm.do_sigma_delta(self, input)
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self.sdm_out = sdm.do_sigma_delta_int(self, input)
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frequency = self._sdm_out_to_freq(self.sdm_out)
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return frequency
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def print_stats(self):
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"""
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Returns a summary of the SDM range and steps.
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"""
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steps = self.p_value + 1 # +1 we have frac off state
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min_freq = self._sdm_out_to_freq(0)
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max_freq = self._sdm_out_to_freq(self.p_value)
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target_output_frequency = self.profiles[self.profile]["output_frequency"]
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ave_step_size = (max_freq - min_freq) / steps
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print(f"SDM min_freq: {min_freq:.0f}Hz")
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print(f"SDM max_freq: {max_freq:.0f}Hz")
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print(f"SDM steps: {steps}")
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print(f"PPM range: {1e6 * (1 - target_output_frequency / min_freq):.6}")
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print(f"PPM range: +{1e6 * (max_freq / target_output_frequency - 1):.6}")
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return min_freq, max_freq, steps
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def plot_freq_range(self):
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"""
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Generates a plot of the frequency range of the LUT and
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visually shows the spacing of the discrete frequencies
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that it can produce.
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"""
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frequencies = []
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for step in range(self.p_value + 1): # +1 since p value is +1 in datasheet
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frequencies.append(self._sdm_out_to_freq(step))
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plt.clf()
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plt.plot(frequencies, color='green', marker='.', label='frequency')
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plt.title('PLL fractional range', fontsize=14)
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plt.xlabel(f'SDM step', fontsize=14)
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plt.ylabel('Frequency', fontsize=10)
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plt.legend(loc="upper right")
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plt.grid(True)
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# plt.show()
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plt.savefig("sdm_dco_range.png", dpi=150)
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def write_register_file(self):
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with open(register_file, "w") as reg_vals:
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reg_vals.write(f"/* Autogenerated SDM App PLL setup by {Path(__file__).name} using {self.profile} profile */\n")
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reg_vals.write(self.app_pll.gen_register_file_text())
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reg_vals.write(f"#define SW_PLL_SDM_CTRL_MID {self.profiles[self.profile]['mod_init']}\n")
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reg_vals.write(f"#define SW_PLL_SDM_RATE {self.profiles[self.profile]['sdm_rate']}\n")
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reg_vals.write("\n\n")
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return register_file
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if __name__ == '__main__':
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"""
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This module is not intended to be run directly. This is here for internal testing only.
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"""
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dco = lut_dco()
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print(f"LUT size: {dco.get_lut_size()}")
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dco.plot_freq_range()
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dco.print_stats(12288000)
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sdm_dco = sigma_delta_dco("24.576_1M")
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sdm_dco.write_register_file()
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sdm_dco.print_stats()
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sdm_dco.plot_freq_range()
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for i in range(30):
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output_frequency = sdm_dco.do_modulate(500000)
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# print(i, output_frequency)
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