2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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# RTL8711DCM Module Design Guide
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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### 1. Wireless Audio Module Control Introduction
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(1) Wireless 2.1 Audio Module Control Diagram
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(2) Wireless 5.1 Audio Module Control Diagram
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(3) Wireless 7.1.2 Audio Module Control Diagram
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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### 2. RTL8711DCM Module PIN Diagram
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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### 3. RTL8711DCM Module Hardware Circuit Control Diagram
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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#### (1) RTL8711DCM Module (TX) **I2S Hardware Control Diagram**
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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##### 1) DSP and RTL8711DCM Module (TX) Stereo I2S Wiring Instructions
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2025-05-14 15:25:41 +08:00
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Slave:
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I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, GND
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2025-05-14 15:25:41 +08:00
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```
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Master:
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I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, GND
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2025-05-14 15:25:41 +08:00
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```
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2025-12-31 18:12:27 +08:00
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##### 2) DSP and RTL8711DCM Module (TX) 5.1 Channel I2S Wiring Instructions
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2025-05-14 15:25:41 +08:00
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Slave:
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I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, I2S_DATA2, GND
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2025-05-14 15:25:41 +08:00
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```
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Master:
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, I2S_DATA2, GND
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2025-05-14 15:25:41 +08:00
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```
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2025-12-31 18:12:27 +08:00
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##### 3) DSP and Wireless Audio RTL8711DCM Module (TX) 7.1.2 Channel I2S Wiring Instructions
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2025-05-14 15:25:41 +08:00
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Slave:
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, I2S_DATA2, I2S_DATA3,
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I2S_EX_LRCLK, I2S_EX_BCLK, I2S_EX_DATA0, GND
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2025-05-14 15:25:41 +08:00
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```
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Master:
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, I2S_DATA2, I2S_DATA3,
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I2S_EX_LRCLK, I2S_EX_BCLK, I2S_EX_DATA0, GND
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2025-05-14 15:25:41 +08:00
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```
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2025-12-31 18:12:27 +08:00
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#### (2) RTL8711DCM Module (TX) Hardware **TDM Control Diagram**
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##### 1) DSP and RTL8711DCM Module (TX) Stereo I2S Wiring Instructions
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2025-05-14 15:25:41 +08:00
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Slave:
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I2S_BCLK, I2S_LRCLK, I2S_DATA0, GND
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2025-05-14 15:25:41 +08:00
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```
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Master:
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I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, GND
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2025-05-14 15:25:41 +08:00
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```
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2025-12-31 18:12:27 +08:00
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##### 2) DSP and RTL8711DCM Module (TX) 5.1 Channel I2S Wiring Instructions
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2025-05-14 15:25:41 +08:00
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Slave:
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I2S_BCLK, I2S_LRCLK, I2S_DATA0, GND
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2025-05-14 15:25:41 +08:00
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```
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Master:
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, GND
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2025-05-14 15:25:41 +08:00
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```
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2025-12-31 18:12:27 +08:00
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##### 3) DSP and Wireless Audio RTL8711DCM Module (TX) 7.1.2 Channel I2S Wiring Instructions
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2025-05-14 15:25:41 +08:00
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Slave:
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_EX_LRCLK,
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I2S_EX_BCLK, I2S_EX_DATA0, GND
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2025-05-14 15:25:41 +08:00
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```
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```note
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2025-12-31 18:12:27 +08:00
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I2S signal lines required when DSP operates as Master:
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0,
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I2S_EX_LRCLK, I2S_EX_BCLK, I2S_EX_DATA0, GND
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2025-05-14 15:25:41 +08:00
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```
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2025-12-31 18:12:27 +08:00
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[//]: # (#### (3) RTL8711DCM Module (TX) Hardware **uart Control Diagram**)
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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[//]: # ()
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2025-05-14 15:25:41 +08:00
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2025-12-31 18:12:27 +08:00
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#### (3) RTL8711DCM Module (RX) Hardware Control Diagram
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2025-05-14 15:25:41 +08:00
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