3.2 KiB
3.2 KiB
RTL8711DCM Module Design Guide
1. Wireless Audio Module Control Introduction
(1) Wireless 2.1 Audio Module Control Diagram
(2) Wireless 5.1 Audio Module Control Diagram
(3) Wireless 7.1.2 Audio Module Control Diagram
2. RTL8711DCM Module PIN Diagram
3. RTL8711DCM Module Hardware Circuit Control Diagram
(1) RTL8711DCM Module (TX) I2S Hardware Control Diagram
1) DSP and RTL8711DCM Module (TX) Stereo I2S Wiring Instructions
I2S signal lines required when DSP operates as Slave:
I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, GND
I2S signal lines required when DSP operates as Master:
I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, GND
2) DSP and RTL8711DCM Module (TX) 5.1 Channel I2S Wiring Instructions
I2S signal lines required when DSP operates as Slave:
I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, I2S_DATA2, GND
I2S signal lines required when DSP operates as Master:
I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, I2S_DATA2, GND
3) DSP and Wireless Audio RTL8711DCM Module (TX) 7.1.2 Channel I2S Wiring Instructions
I2S signal lines required when DSP operates as Slave:
I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, I2S_DATA2, I2S_DATA3,
I2S_EX_LRCLK, I2S_EX_BCLK, I2S_EX_DATA0, GND
I2S signal lines required when DSP operates as Master:
I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_DATA1, I2S_DATA2, I2S_DATA3,
I2S_EX_LRCLK, I2S_EX_BCLK, I2S_EX_DATA0, GND
(2) RTL8711DCM Module (TX) Hardware TDM Control Diagram
1) DSP and RTL8711DCM Module (TX) Stereo I2S Wiring Instructions
I2S signal lines required when DSP operates as Slave:
I2S_BCLK, I2S_LRCLK, I2S_DATA0, GND
I2S signal lines required when DSP operates as Master:
I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, GND
2) DSP and RTL8711DCM Module (TX) 5.1 Channel I2S Wiring Instructions
I2S signal lines required when DSP operates as Slave:
I2S_BCLK, I2S_LRCLK, I2S_DATA0, GND
I2S signal lines required when DSP operates as Master:
I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0, GND
3) DSP and Wireless Audio RTL8711DCM Module (TX) 7.1.2 Channel I2S Wiring Instructions
I2S signal lines required when DSP operates as Slave:
I2S_BCLK, I2S_LRCLK, I2S_DATA0, I2S_EX_LRCLK,
I2S_EX_BCLK, I2S_EX_DATA0, GND
I2S signal lines required when DSP operates as Master:
I2S_MCLK, I2S_BCLK, I2S_LRCLK, I2S_DATA0,
I2S_EX_LRCLK, I2S_EX_BCLK, I2S_EX_DATA0, GND
//: # (#### (3) RTL8711DCM Module (TX) Hardware uart Control Diagram)
(3) RTL8711DCM Module (RX) Hardware Control Diagram
